ROM_CTRL/32KB Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: c9ef9e5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.200s	185.871us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.240s	140.898us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.170s	559.048us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.090s	130.200us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.550s	290.903us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.960s	174.479us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.170s	559.048us	20	20	100.00
		rom_ctrl_csr_aliasing	6.550s	290.903us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.540s	132.487us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.680s	170.629us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.400s	468.103us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	30.710s	600.715us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	11.610s	319.198us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.930s	558.707us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.120s	188.421us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.120s	188.421us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.240s	140.898us	5	5	100.00
		rom_ctrl_csr_rw	7.170s	559.048us	20	20	100.00
		rom_ctrl_csr_aliasing	6.550s	290.903us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.620s	175.803us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.240s	140.898us	5	5	100.00
		rom_ctrl_csr_rw	7.170s	559.048us	20	20	100.00
		rom_ctrl_csr_aliasing	6.550s	290.903us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.620s	175.803us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.190m	2.616ms	3	20	15.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	24.210s	3.188ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	5.044m	1.909ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.010m	986.391us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	5.044m	1.909ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	5.044m	1.909ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.190m	2.616ms	3	20	15.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.190m	2.616ms	3	20	15.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.190m	2.616ms	3	20	15.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.190m	2.616ms	3	20	15.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.190m	2.616ms	3	20	15.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	5.044m	1.909ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	5.044m	1.909ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.200s	185.871us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.200s	185.871us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.200s	185.871us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.010m	986.391us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.190m	2.616ms	3	20	15.00
		rom_ctrl_kmac_err_chk	11.610s	319.198us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.190m	2.616ms	3	20	15.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.190m	2.616ms	3	20	15.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.190m	2.616ms	3	20	15.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	24.210s	3.188ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	5.044m	1.909ms	5	5	100.00
V2S		TOTAL			48	65	73.85
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.242m	13.696ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			249	266	93.61

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.68	100.00	99.41	100.00	93.33	100.00	98.97	99.05

Failure Buckets

• Job timed out after * minutes has 14 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 14 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.68602361840133277112714682787290034623495850597191422332188604895345680248578
      Log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        Job timed out after 60 minutes
      

    • 2.rom_ctrl_corrupt_sig_fatal_chk.92406864695480035472588773492016442660224405156043727350100640718504405204347
      Log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 12 more failures.

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.

    • 3.rom_ctrl_corrupt_sig_fatal_chk.71857580860627628326031512383399355325361165380447848705306117485007873310318
      Line 81, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 5749148116 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 5749148116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.rom_ctrl_corrupt_sig_fatal_chk.115150367558595952043024224900056516499347357357504334207059818785460655490219
      Line 85, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 573739926 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 573739926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.