ROM_CTRL/64KB Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: c9ef9e5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 13.840s 1.034ms 2 2 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 13.670s 1.082ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 14.610s 1.071ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 11.050s 295.020us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 10.980s 295.833us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 11.400s 310.236us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 14.610s 1.071ms 20 20 100.00
rom_ctrl_csr_aliasing 10.980s 295.833us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 9.870s 373.411us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 12.520s 297.601us 5 5 100.00
V1 TOTAL 67 67 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 11.380s 824.814us 2 2 100.00
V2 stress_all rom_ctrl_stress_all 52.850s 10.061ms 20 20 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 21.820s 711.027us 2 2 100.00
V2 alert_test rom_ctrl_alert_test 14.910s 1.039ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 16.800s 292.000us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 16.800s 292.000us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 13.670s 1.082ms 5 5 100.00
rom_ctrl_csr_rw 14.610s 1.071ms 20 20 100.00
rom_ctrl_csr_aliasing 10.980s 295.833us 5 5 100.00
rom_ctrl_same_csr_outstanding 14.500s 225.241us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 13.670s 1.082ms 5 5 100.00
rom_ctrl_csr_rw 14.610s 1.071ms 20 20 100.00
rom_ctrl_csr_aliasing 10.980s 295.833us 5 5 100.00
rom_ctrl_same_csr_outstanding 14.500s 225.241us 20 20 100.00
V2 TOTAL 114 114 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.667m 3.113ms 4 20 20.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 1.240m 23.730ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 10.723m 2.142ms 5 5 100.00
rom_ctrl_tl_intg_err 1.722m 2.144ms 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 10.723m 2.142ms 5 5 100.00
V2S prim_count_check rom_ctrl_sec_cm 10.723m 2.142ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.667m 3.113ms 4 20 20.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.667m 3.113ms 4 20 20.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.667m 3.113ms 4 20 20.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.667m 3.113ms 4 20 20.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.667m 3.113ms 4 20 20.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 10.723m 2.142ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 10.723m 2.142ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 13.840s 1.034ms 2 2 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 13.840s 1.034ms 2 2 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 13.840s 1.034ms 2 2 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.722m 2.144ms 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.667m 3.113ms 4 20 20.00
rom_ctrl_kmac_err_chk 21.820s 711.027us 2 2 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.667m 3.113ms 4 20 20.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.667m 3.113ms 4 20 20.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.667m 3.113ms 4 20 20.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 1.240m 23.730ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 10.723m 2.142ms 5 5 100.00
V2S TOTAL 49 65 75.38
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.570m 15.504ms 20 20 100.00
V3 TOTAL 20 20 100.00
TOTAL 250 266 93.98

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.45 99.87 98.68 100.00 93.33 99.28 98.97 99.05

Failure Buckets