RV_TIMER Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: c9ef9e5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.170s	10.748us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.160s	48.431us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.190s	18.552us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.050s	194.970us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.300s	27.425us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.890s	146.798us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.190s	18.552us	20	20	100.00
		rv_timer_csr_aliasing	2.300s	27.425us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	12.570s	26.697ms	20	20	100.00
V2	disabled	rv_timer_disabled	7.850s	2.687ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	7.987m	520.640ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	7.987m	520.640ms	10	10	100.00
V2	stress	rv_timer_stress_all	8.970s	4.342ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.140s	14.709us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.210s	14.546us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.980s	421.612us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.980s	421.612us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.160s	48.431us	5	5	100.00
		rv_timer_csr_rw	2.190s	18.552us	20	20	100.00
		rv_timer_csr_aliasing	2.300s	27.425us	5	5	100.00
		rv_timer_same_csr_outstanding	2.340s	431.171us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.160s	48.431us	5	5	100.00
		rv_timer_csr_rw	2.190s	18.552us	20	20	100.00
		rv_timer_csr_aliasing	2.300s	27.425us	5	5	100.00
		rv_timer_same_csr_outstanding	2.340s	431.171us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.510s	150.362us	5	5	100.00
		rv_timer_tl_intg_err	3.130s	1.323ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.130s	1.323ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.101m	23.274ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	2.090s	18.479us	10	10	100.00
		rv_timer_max	2.100s	15.797us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00