SPI_DEVICE/1R1W Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: `c9ef9e5`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.261m	51.725ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.480s	32.686us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.670s	140.293us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.130s	2.759ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.940s	644.889us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.310s	1.864ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.670s	140.293us	20	20	100.00
		spi_device_csr_aliasing	15.940s	644.889us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.760s	15.065us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.700s	243.895us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.410s	15.367us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.330s	1.642us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.760s	1.142us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	9.330s	204.817us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.330s	204.817us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.370s	16.208ms	50	50	100.00
		spi_device_tpm_sts_read	2.640s	109.114us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	55.260s	14.890ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	42.710s	12.483ms	50	50	100.00
		spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.060s	35.873ms	50	50	100.00
		spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.060s	35.873ms	50	50	100.00
		spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	43.500s	3.882ms	50	50	100.00
		spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	43.500s	3.882ms	50	50	100.00
		spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	43.500s	3.882ms	50	50	100.00
		spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	43.500s	3.882ms	50	50	100.00
		spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	43.500s	3.882ms	50	50	100.00
		spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.830s	14.896ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.306m	34.951ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.306m	34.951ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.306m	34.951ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	49.980s	23.263ms	50	50	100.00
		spi_device_read_buffer_direct	20.450s	6.079ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.306m	34.951ms	50	50	100.00
		spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.452m	117.989ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	22.520s	5.348ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	22.520s	5.348ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.261m	51.725ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.070m	227.454ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.671m	277.283ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.340s	12.992us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.150s	29.189us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.750s	401.348us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.750s	401.348us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.480s	32.686us	5	5	100.00
		spi_device_csr_rw	3.670s	140.293us	20	20	100.00
		spi_device_csr_aliasing	15.940s	644.889us	5	5	100.00
		spi_device_same_csr_outstanding	5.580s	661.552us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.480s	32.686us	5	5	100.00
		spi_device_csr_rw	3.670s	140.293us	20	20	100.00
		spi_device_csr_aliasing	15.940s	644.889us	5	5	100.00
		spi_device_same_csr_outstanding	5.580s	661.552us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.600s	536.650us	5	5	100.00
		spi_device_tl_intg_err	20.330s	852.816us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.330s	852.816us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.561m	64.652ms	49	50	98.00
		TOTAL			1129	1151	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.44	98.98	96.22	83.25	89.36	98.39	95.66	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.36427070426096554499873509041668062526358954800695405893876272514447936362831
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1759532 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[96])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1759532 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1759532 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[992])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.51316716215171789107175040698943791060413924598353475710848904063322409912181
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4013806 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[16])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4013806 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4013806 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[912])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.17920414360772418434421183475474491077614188463706654934478168218415941662875
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @    704918 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    704918 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
  UVM_ERROR @    707918 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x73fbca [11100111111101111001010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
  UVM_ERROR @    707918 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x73fbca [11100111111101111001010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

21.spi_device_flash_mode_ignore_cmds.70551947888143783990843447585226159331717272205847307584680953512631607754122
Line 77, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 10254120816 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0x210c8c
  tl_ul_fuzzy_flash_status_q[i] = 0x27ef46
  UVM_INFO @ 13614468170 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/4
  UVM_INFO @ 13614468170 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/4