SPI_HOST Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: c9ef9e5

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.267m	12.980ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	15.956us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	15.376us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	606.139us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	16.608us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	40.771us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	15.376us	20	20	100.00
		spi_host_csr_aliasing	5.000s	16.608us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	17.331us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	16.672us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	6.000s	69.230us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	21.000s	331.785us	50	50	100.00
		spi_host_error_cmd	5.000s	18.564us	50	50	100.00
		spi_host_event	13.433m	68.047ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.850m	200.000ms	49	50	98.00
V2	speed	spi_host_speed	6.850m	200.000ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	6.850m	200.000ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	2.083m	5.682ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	76.230us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.850m	200.000ms	49	50	98.00
V2	full_cycle	spi_host_speed	6.850m	200.000ms	49	50	98.00
V2	duplex	spi_host_smoke	2.267m	12.980ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.267m	12.980ms	50	50	100.00
V2	stress_all	spi_host_stress_all	36.800m	1.000s	48	50	96.00
V2	spien	spi_host_spien	4.050m	12.422ms	50	50	100.00
V2	stall	spi_host_status_stall	24.083m	133.065ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	28.000s	1.445ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	21.000s	331.785us	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	27.762us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	46.212us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	599.541us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	599.541us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	15.956us	5	5	100.00
		spi_host_csr_rw	5.000s	15.376us	20	20	100.00
		spi_host_csr_aliasing	5.000s	16.608us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	57.982us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	15.956us	5	5	100.00
		spi_host_csr_rw	5.000s	15.376us	20	20	100.00
		spi_host_csr_aliasing	5.000s	16.608us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	57.982us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	105.106us	20	20	100.00
		spi_host_sec_cm	5.000s	170.089us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	105.106us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.083m	33.254ms	9	10	90.00
		TOTAL			836	840	99.52

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.31	96.78	93.27	98.69	94.47	88.02	100.00	97.27	91.56

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

  • Test spi_host_stress_all has 2 failures.

    • 4.spi_host_stress_all.2433823796112025501388880832793242992818282533875073462731364857817178143123
      Line 194, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/4.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 27.spi_host_stress_all.67291180571804439803929130210281031828235632411812849276485797817313058347255
      Line 294, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/27.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 6.spi_host_upper_range_clkdiv.96023752615554427248860861451544727073598042692371736202209905712719438998164
      Line 129, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_speed has 1 failures.

    • 24.spi_host_speed.32954484079400293649284704406641265062643949346289756502281459178995131090255
      Line 151, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/24.spi_host_speed/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---