SRAM_CTRL/MAIN Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: c9ef9e5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.624m	1.589ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.160s	199.602us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.260s	20.665us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.580s	253.976us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.270s	239.632us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.430s	2.501ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.260s	20.665us	20	20	100.00
		sram_ctrl_csr_aliasing	2.270s	239.632us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.940m	20.706ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.924m	27.582ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	21.471m	29.587ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.684m	11.373ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	39.124m	151.393ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.049m	80.204ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.825m	47.529ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.937m	139.561ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.812m	2.584ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.887m	21.171ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.392m	3.163ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.486m	794.452us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.879m	1.889ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.249m	18.210ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.190s	3.043ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.897h	347.510ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.190s	57.674us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.120s	44.269us	19	20	95.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.120s	44.269us	19	20	95.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.160s	199.602us	5	5	100.00
		sram_ctrl_csr_rw	2.260s	20.665us	20	20	100.00
		sram_ctrl_csr_aliasing	2.270s	239.632us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.260s	93.003us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.160s	199.602us	5	5	100.00
		sram_ctrl_csr_rw	2.260s	20.665us	20	20	100.00
		sram_ctrl_csr_aliasing	2.270s	239.632us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.260s	93.003us	20	20	100.00
V2		TOTAL			788	790	99.75
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.197m	7.493ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.280s	9.390us	0	5	0.00
		sram_ctrl_tl_intg_err	4.350s	340.141us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.280s	9.390us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.350s	340.141us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.249m	18.210ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.249m	18.210ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.260s	20.665us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.937m	139.561ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.937m	139.561ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.937m	139.561ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.825m	47.529ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	10.910s	2.799ms	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.197m	7.493ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	12.310s	13.139ms	37	50	74.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.624m	1.589ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.624m	1.589ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.937m	139.561ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.280s	9.390us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.825m	47.529ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.280s	9.390us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.280s	9.390us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.624m	1.589ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.280s	9.390us	0	5	0.00
V2S		TOTAL			122	145	84.14
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.329m	2.604ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1165	1190	97.90

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.09	99.29	93.01	85.18	100.00	98.03	98.59	98.52

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 13 failures:

  • Test sram_ctrl_readback_err has 13 failures.

    • 2.sram_ctrl_readback_err.107923875071131680118246980773024609945654112402418888219835059053794451756061
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 684755753 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x29) != exp (0x3)
        UVM_INFO @ 684755753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_readback_err.36262145162623094349771416937184594682980106185250862095027380750429428065856
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2631233336 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0xe) != exp (0x37)
        UVM_INFO @ 2631233336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 11 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:

  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 7.sram_ctrl_mubi_enc_err.45030339208849643512266619987112567208468878429640870592088174860685609737648
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2740220843 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2740220843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 15.sram_ctrl_mubi_enc_err.39939023704364702147451877194337215712001748457762335283361202146855694567606
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/15.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 855635806 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 855635806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• Offending '(!$isunknown(rdata_o))' has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 1.sram_ctrl_sec_cm.72753348883303967976733894312313979698541244678043679319840270646360804985300
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1079482 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1079482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.60422889917148876729784686562088954096645795103068932837510130341535855020411
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   5050330 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   5050330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(depth_o <= *'(Depth))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.55448317474490646082704278569000699393942765907202018690957899929019048477659
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3884017 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3884017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.79382284943255084760589462802941909685839533563863128271326884968078475039004
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   9389565 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   9389565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((pend_req[*].pend == *'b0) || $test$plusargs("disable_assert_final_checks"))' has 1 failures:

  • Test sram_ctrl_tl_errors has 1 failures.

    • 1.sram_ctrl_tl_errors.40268630819359526369579329352201401745605676417724697677448716004960928073493
      Line 130, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_errors/latest/run.log

            Offending '((pend_req[84].pend == 1'b0) || $test$plusargs("disable_assert_final_checks"))'
        UVM_ERROR @  44269432 ps: (tlul_assert.sv:301) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
        UVM_INFO @  44269432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 14.sram_ctrl_bijection.111734369135084496198407017245349502442232652724351715818611253356461953405221
      Line 91, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/14.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---