SRAM_CTRL/RET Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: c9ef9e5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	55.220s	128.031us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.150s	62.452us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.220s	29.311us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.480s	597.266us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.170s	21.951us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.780s	163.542us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.220s	29.311us	20	20	100.00
		sram_ctrl_csr_aliasing	2.170s	21.951us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.650s	3.872ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.000s	363.780us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	24.081m	30.166ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.470m	7.851ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.633m	59.387ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	19.243m	4.931ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.120s	7.411ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.129m	71.467ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.749m	744.035us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.048m	21.619ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.623m	283.287us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.680m	612.562us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.694m	1.157ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.805m	14.397ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.270s	34.475us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.303h	45.469ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.150s	37.593us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.740s	518.588us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.740s	518.588us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.150s	62.452us	5	5	100.00
		sram_ctrl_csr_rw	2.220s	29.311us	20	20	100.00
		sram_ctrl_csr_aliasing	2.170s	21.951us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.310s	22.060us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.150s	62.452us	5	5	100.00
		sram_ctrl_csr_rw	2.220s	29.311us	20	20	100.00
		sram_ctrl_csr_aliasing	2.170s	21.951us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.310s	22.060us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.360s	3.279ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.000s	5.086us	0	5	0.00
		sram_ctrl_tl_intg_err	4.250s	341.042us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.000s	5.086us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.250s	341.042us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.805m	14.397ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.805m	14.397ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.220s	29.311us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.129m	71.467ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.129m	71.467ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.129m	71.467ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.120s	7.411ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.660s	170.261us	41	50	82.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.360s	3.279ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.650s	54.350us	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	55.220s	128.031us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	55.220s	128.031us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.129m	71.467ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.000s	5.086us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.120s	7.411ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.000s	5.086us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.000s	5.086us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	55.220s	128.031us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.000s	5.086us	0	5	0.00
V2S		TOTAL			121	145	83.45
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.416m	38.014ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1164	1190	97.82

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.26	93.01	85.10	100.00	97.99	98.58	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 10 failures:

  • Test sram_ctrl_readback_err has 10 failures.

    • 14.sram_ctrl_readback_err.23557857087476245645450501693810955817238313972204661392010689189899944559463
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/14.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 115405794 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x78) != exp (0x3)
        UVM_INFO @ 115405794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 17.sram_ctrl_readback_err.25502002996458271567296448979247253834562718638840623325798327090804261375520
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  53175725 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x63) != exp (0x2d)
        UVM_INFO @  53175725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending 'reqfifo_rvalid' has 9 failures:

  • Test sram_ctrl_mubi_enc_err has 9 failures.

    • 0.sram_ctrl_mubi_enc_err.54057780539599255351020630378958878581281896147499115178436757721714212124689
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  55383154 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  55383154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_mubi_enc_err.56214402906774461964282822164187759009017041337680017754996155368208593858801
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  27676513 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  27676513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• Offending '(!$isunknown(rdata_o))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 1.sram_ctrl_sec_cm.85719552507890374904299250167837269994344114369129442792716854279236032736531
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   9569744 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   9569744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.81747946314078573589190783877198858132440942155846394298435466000891367883476
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   5085573 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   5085573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 3.sram_ctrl_sec_cm.36760036514623626631160493744411004289054470318830358549491314919101237955364
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8394405 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8394405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.90448866385438078428893391000428493624571487781959435379851183003259237452699
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7857776 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7857776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.111013872600628724229117636972188606480549832232009723160353059485139028315730
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   3044720 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   3044720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 2.sram_ctrl_csr_mem_rw_with_rand_reset.67784845262689383314704388813076245613429615877985694264331604935523996539903
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  93041422 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @  93041422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 8.sram_ctrl_csr_mem_rw_with_rand_reset.31129779573527384946518339523414088440631333272654625129199373381560077737452
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  47691392 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
        UVM_INFO @  47691392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---