UART Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: c9ef9e5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	29.630s	6.092ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.330s	80.263us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.380s	24.235us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.870s	241.623us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.420s	38.476us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.640s	83.393us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.380s	24.235us	20	20	100.00
		uart_csr_aliasing	2.420s	38.476us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.362m	92.079ms	50	50	100.00
V2	parity	uart_smoke	29.630s	6.092ms	50	50	100.00
		uart_tx_rx	4.362m	92.079ms	50	50	100.00
V2	parity_error	uart_intr	5.488m	268.604ms	50	50	100.00
		uart_rx_parity_err	9.756m	246.391ms	49	50	98.00
V2	watermark	uart_tx_rx	4.362m	92.079ms	50	50	100.00
		uart_intr	5.488m	268.604ms	50	50	100.00
V2	fifo_full	uart_fifo_full	4.970m	127.380ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.945m	108.060ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	5.407m	63.434ms	300	300	100.00
V2	rx_frame_err	uart_intr	5.488m	268.604ms	50	50	100.00
V2	rx_break_err	uart_intr	5.488m	268.604ms	50	50	100.00
V2	rx_timeout	uart_intr	5.488m	268.604ms	50	50	100.00
V2	perf	uart_perf	16.108m	23.834ms	50	50	100.00
V2	sys_loopback	uart_loopback	30.300s	9.735ms	50	50	100.00
V2	line_loopback	uart_loopback	30.300s	9.735ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.578m	101.988ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.781m	41.898ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	48.050s	13.053ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	55.980s	5.708ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	18.462m	163.130ms	50	50	100.00
V2	stress_all	uart_stress_all	26.355m	547.141ms	50	50	100.00
V2	alert_test	uart_alert_test	2.200s	11.830us	50	50	100.00
V2	intr_test	uart_intr_test	2.320s	13.879us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	4.220s	137.730us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	4.220s	137.730us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.330s	80.263us	5	5	100.00
		uart_csr_rw	2.380s	24.235us	20	20	100.00
		uart_csr_aliasing	2.420s	38.476us	5	5	100.00
		uart_same_csr_outstanding	2.420s	49.837us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.330s	80.263us	5	5	100.00
		uart_csr_rw	2.380s	24.235us	20	20	100.00
		uart_csr_aliasing	2.420s	38.476us	5	5	100.00
		uart_same_csr_outstanding	2.420s	49.837us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	2.460s	316.087us	5	5	100.00
		uart_tl_intg_err	3.160s	94.690us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.160s	94.690us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.445m	5.010ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1316	1320	99.70

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.17	98.25	91.55	--	98.14	100.00	99.48

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 2 failures:

  • Test uart_rx_parity_err has 1 failures.

    • 23.uart_rx_parity_err.112047811949824816203800474358720860273257841015925118437701770598267595356376
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/23.uart_rx_parity_err/latest/run.log

        UVM_ERROR @   2938504 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 1703765457 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 1/6
        UVM_INFO @ 6022140290 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 2/6
        UVM_INFO @ 82743052141 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 3/6
        UVM_INFO @ 91364080869 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 4/6
      

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 37.uart_stress_all_with_rand_reset.106755640385473913846125763077881425957475224886229226811629949953202558155114
      Line 177, in log /nightly/runs/scratch/master/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6522652021 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 6541424564 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 9/10
        UVM_INFO @ 6541543614 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 9/10
      

• UVM_ERROR (cip_base_vseq.sv:832) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 4.uart_stress_all_with_rand_reset.96691139277712445352701592469835590180090547052315802538722529348891643407945
      Line 100, in log /nightly/runs/scratch/master/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14060666975 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 14060666975 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 4/5
        UVM_INFO @ 14061000309 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 4/5
      

• UVM_ERROR (cip_base_vseq.sv:928) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 78.uart_stress_all_with_rand_reset.44540705475622002080108536757533832438041271170720913769248088789988514987058
      Line 123, in log /nightly/runs/scratch/master/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2575961893 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 2575971225 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2575971225 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 5/5
        UVM_INFO @ 2575978842 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2