CHIP Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: `c9ef9e5`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.815m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.815m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.297m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	54.800s		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.298m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.418m	6.096ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.418m	6.096ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.418m	6.096ms	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	52.100s	10.340us	0	3	0.00
		chip_sw_example_manufacturer	3.298m		0	3	0.00
		chip_sw_example_concurrency	7.054m	5.223ms	3	3	100.00
		chip_sw_uart_smoketest_signed	23.816s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	18.590s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	17.790s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	17.790s		0	3	0.00
V1	xbar_smoke	xbar_smoke	36.260s	72.610us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.912m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.811m	8.731ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	7.793m	4.584ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	24.114s		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	24.531s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	36.442s		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	23.645s		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	5.390s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.390s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.166m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	4.145m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.935m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.935m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.035m	4.973ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	4.393m	3.273ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.599m	15.585ms	0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	18.486s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	15.984s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	22.824m	22.094ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	8.032m	6.345ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	33.465m	18.016ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	33.465m	18.016ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	17.619s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.716m	5.975ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.716m	5.975ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.760m	18.017ms	0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.890m	4.128ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.900m	5.900ms	3	3	100.00
		chip_sw_aes_idle	6.496m	5.983ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.668m	5.864ms	3	3	100.00
		chip_sw_kmac_idle	5.840m	5.250ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	18.168s		0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	16.382s		0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	18.610s		0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	18.201s		0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	18.254s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.434s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.693s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.541s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	17.978s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.197s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.388s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.254s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.434s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.693s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.541s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	17.978s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.197s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.388s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.821s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.137m	10.220us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.173m	10.200us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.337m	10.260us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.302m	10.300us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	20.776s		0	3	0.00
		chip_sw_clkmgr_jitter	4.660m	3.235ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.889m	4.666ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	18.578s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.259m	10.400us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.073m	10.300us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1.285m	10.280us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.191m	10.300us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.052m	10.320us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	23.320s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	18.541s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	18.872s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	16.428s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	34.702m	16.552ms	89	100	89.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	14.881m	16.259ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	7.716m	5.975ms	0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	18.621s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	14.881m	16.259ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	21.864s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	21.339s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	19.054s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	20.409s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	59.773s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	34.702m	16.552ms	89	100	89.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.599m	15.585ms	0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	38.784m	20.015ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.546m	6.808ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.410m	30.016ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.764m	4.349ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	34.702m	16.552ms	89	100	89.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	20.328s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	19.990s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	34.702m	16.552ms	89	100	89.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	19.190s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.410m	30.016ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	18.244s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	23.388s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	18.934s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.811s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	19.434s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	17.742s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	19.990s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	21.783s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.233s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	21.783s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	21.783s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	21.783s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	9.533m	7.539ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	28.444s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	21.548s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	22.492s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	19.056s		0	3	0.00
		chip_sw_lc_ctrl_transition	21.783s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	10.321m	9.745ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	14.996m	12.674ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	20.764s		0	3	0.00
		chip_prim_tl_access	20.681m	18.683ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.254s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.434s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.693s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.541s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	17.978s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.197s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.388s		0	3	0.00
		chip_rv_dm_lc_disabled	22.824m	22.094ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.442m	5.543ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	1.137m	10.220us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.417m	3.776ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	6.496m	5.983ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.473m	5.348ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	1.173m	10.200us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.668m	5.864ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.478m	3.918ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.960m	5.833ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.302m	10.300us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	10.321m	9.745ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	21.783s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.139m	10.400us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	8.376m	4.955ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.840m	5.250ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	20.437s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	20.437s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	17.183s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.710m	5.383ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	18.805s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	10.321m	9.745ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.337m	10.260us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	18.349s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	18.821s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.900m	5.900ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.900m	5.900ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.900m	5.900ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	10.437m	5.319ms	3	3	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	14.996m	12.674ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	14.996m	12.674ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.865m	9.879ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	20.776s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	20.764s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	34.702m	16.552ms	89	100	89.00
		chip_sw_data_integrity_escalation	2.935m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	21.783s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	10.437m	5.319ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	10.321m	9.745ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	11.865m	9.879ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.757m	4.152ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	10.437m	5.319ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	10.321m	9.745ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	11.865m	9.879ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.757m	4.152ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	21.783s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	19.114s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.233s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	28.444s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	21.548s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	22.492s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	19.056s		0	3	0.00
		chip_sw_lc_ctrl_transition	21.783s		0	15	0.00
		chip_prim_tl_access	20.681m	18.683ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	20.681m	18.683ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	23.198s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	15.711s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	18.541s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.821s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.137m	10.220us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.173m	10.200us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.337m	10.260us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.302m	10.300us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	20.776s		0	3	0.00
		chip_sw_clkmgr_jitter	4.660m	3.235ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	5.802m	4.357ms	0	3	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	5.802m	4.357ms	0	3	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	6.925m	4.231ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	5.717m	4.429ms	0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	6.253m	5.234ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	9.762m	5.822ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.859m	3.925ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	6.015m	5.406ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	5.757m	4.152ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	38.784m	20.015ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	38.784m	20.015ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	6.192m	5.159ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.415m	5.905ms	3	3	100.00
		chip_sw_clkmgr_smoketest	6.098m	5.434ms	3	3	100.00
		chip_sw_csrng_smoketest	6.019m	4.753ms	3	3	100.00
		chip_sw_gpio_smoketest	6.458m	4.152ms	3	3	100.00
		chip_sw_hmac_smoketest	8.202m	5.161ms	3	3	100.00
		chip_sw_kmac_smoketest	6.629m	3.590ms	3	3	100.00
		chip_sw_otbn_smoketest	8.567m	4.979ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.162m	5.340ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.724m	4.869ms	3	3	100.00
		chip_sw_rv_timer_smoketest	9.880m	5.878ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.659m	4.910ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.950m	3.701ms	3	3	100.00
		chip_sw_uart_smoketest	6.963m	5.702ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	23.769s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	23.816s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.912m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	17.891s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.630m	6.411ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.740m	4.039ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.253m	3.806ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.814m	5.171ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	32.184s		0	3	0.00
		chip_rv_dm_lc_disabled	22.824m	22.094ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	19.050s		0	3	0.00
		chip_sw_lc_walkthrough_prod	17.480s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	18.753s		0	3	0.00
		chip_sw_lc_walkthrough_rma	25.723s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	32.184s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	22.397s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	18.353s		0	3	0.00
		rom_volatile_raw_unlock	54.016s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	41.835s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.619m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.088m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	5.827m	5.027ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	5.827m	5.027ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	17.790s		0	3	0.00
		chip_same_csr_outstanding	14.010s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	17.790s		0	3	0.00
		chip_same_csr_outstanding	14.010s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	4.884m	474.747us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	15.840s	13.403us	100	100	100.00
		xbar_smoke_large_delays	9.298m	2.599ms	100	100	100.00
		xbar_smoke_slow_rsp	10.710m	2.090ms	100	100	100.00
		xbar_random_zero_delays	2.180m	71.229us	100	100	100.00
		xbar_random_large_delays	38.538m	14.121ms	100	100	100.00
		xbar_random_slow_rsp	58.775m	14.986ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.880m	251.376us	100	100	100.00
		xbar_error_and_unmapped_addr	2.440m	223.647us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	4.687m	509.153us	100	100	100.00
		xbar_error_and_unmapped_addr	2.440m	223.647us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	7.121m	828.143us	100	100	100.00
		xbar_access_same_device_slow_rsp	57.453m	16.905ms	75	100	75.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	3.706m	449.610us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	27.471m	3.202ms	100	100	100.00
		xbar_stress_all_with_error	26.521m	3.104ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	55.764m	1.924ms	96	100	96.00
		xbar_stress_all_with_reset_error	42.061m	5.317ms	97	100	97.00
V2	rom_e2e_smoke	rom_e2e_smoke	17.908s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	17.851s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	18.250s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	17.786s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	16.930s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	17.293s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	16.316s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	18.228s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.009s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	15.950s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.554s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.301s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.407s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.414s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.314s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.374s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	15.541s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	15.348s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.478s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.459s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	14.087s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.965s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.519s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.789s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.136s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	14.515s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	14.092s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.261s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.775s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.125s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.388s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.302s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	15.670s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	18.195s		0	3	0.00
		rom_e2e_asm_init_dev	15.892s		0	3	0.00
		rom_e2e_asm_init_prod	17.785s		0	3	0.00
		rom_e2e_asm_init_prod_end	17.666s		0	3	0.00
		rom_e2e_asm_init_rma	18.196s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	18.739s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	17.730s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	18.073s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	18.532s		0	3	0.00
V2		TOTAL			1889	2429	77.77
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.591m	5.660ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.400m	3.677ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	14.943s		0	1	0.00
		rom_e2e_jtag_debug_dev	16.962s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.796s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	19.277s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	34.702m	16.552ms	89	100	89.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.052m		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	24.416m	12.998ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	15.577s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	24.258s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	14.943s		0	1	0.00
		rom_e2e_jtag_debug_dev	16.962s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.796s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	17.457s		0	1	0.00
		rom_e2e_jtag_inject_dev	17.847s		0	1	0.00
		rom_e2e_jtag_inject_rma	17.306s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.842m		0	3	0.00
V3		TOTAL			1	20	5.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	29.055m	12.678ms	3	3	100.00
		chip_plic_all_irqs_0	14.823m	7.742ms	3	3	100.00
		chip_plic_all_irqs_10	14.065m	6.767ms	3	3	100.00
		chip_sw_dma_inline_hashing	6.562m	3.971ms	3	3	100.00
		chip_sw_dma_abort	6.129m	4.706ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	15.313s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	16.991s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	16.743s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	19.146s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	17.169s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	17.642s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	16.561s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	17.168s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	1.424m		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	19.625s		0	3	0.00
		chip_sw_mbx_smoketest	6.673m	6.069ms	3	3	100.00
		TOTAL			2017	2659	75.86

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
75.46	74.45	78.12	65.80	--	80.89	66.93	86.56

Failure Buckets

Job returned non-zero exit code has 467 failures:

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.79182351359907395326999604158459137687796064280836354086749379244319200431289
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (fbab3d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 174.387s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_manufacturer.54143426150636059437793789659791781618741898825934571501594047181635501692261
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (2db1b4)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 4.218s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_data_integrity_escalation has 6 failures.

0.chip_sw_data_integrity_escalation.58408253580023412683923582695083308858696003558335533077460253369560973203260
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (344ace)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 160.329s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_data_integrity_escalation.83579326229232619433968497733912034574708277216322024261833365572966822033818
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (21b0b8)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 20.299s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 4 more failures.

Test chip_sw_sleep_pin_wake has 3 failures.

0.chip_sw_sleep_pin_wake.6612304678611283866058401856275888803767017968028075301893841969826941691560
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (1f418d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 172.162s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_wake.22924174813881198610631132510828817819563869249549200317201619791113089303679
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (8d51a9)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 9.732s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_sleep_pin_retention has 3 failures.

0.chip_sw_sleep_pin_retention.19893257212123732560385736864847155379368204069796376508676338504464080727815
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (6a6a51)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 232.950s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_retention.96608723435913105473196656944639412206448224349020609718875091003709310283089
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (d91d76)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 6.246s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_uart_tx_rx has 5 failures.

0.chip_sw_uart_tx_rx.3576502427916869660753347498427696991679720271916454818307790349877916156731
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (8c9b4f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 151.840s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_uart_tx_rx.21632073779198864297175617897888756802877231301897211511671374207450757589827
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (e09462)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 31.762s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 3 more failures.

... and 135 more tests.

Job timed out after * minutes has 32 failures:
- Test xbar_access_same_device_slow_rsp has 25 failures.
  - 8.xbar_access_same_device_slow_rsp.10953091630230514829893221936837436559017289715040969321345081087669434822590
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - 10.xbar_access_same_device_slow_rsp.5780269912392933730477743067256128342291269788457444023404141929764555607112
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 23 more failures.
- Test xbar_stress_all_with_reset_error has 3 failures.
  - 9.xbar_stress_all_with_reset_error.91690706234725247032368711104188734394347583071491896529211424814576118533331
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_stress_all_with_reset_error/latest/run.log
```
  Job timed out after 60 minutes
```
  - 50.xbar_stress_all_with_reset_error.16832602895584606732415301005425648500777052665646799153451917384783730167106
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/50.xbar_stress_all_with_reset_error/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test xbar_stress_all_with_rand_reset has 4 failures.
  - 46.xbar_stress_all_with_rand_reset.41885714340698394912031304104909128549237772620645432298718285506815139207250
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - 53.xbar_stress_all_with_rand_reset.40325068084590268091387576401731503105859671554850893309438529623190428314651
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/53.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 2 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 27 failures:
- Test chip_sw_aes_enc_jitter_en has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en.68069801060863278950319420873652948482002216537734539038377280468880631251
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en.56668051387167944422525374885853104018378819668557710615309522661335575194030
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_hmac_enc_jitter_en has 3 failures.
  - 0.chip_sw_hmac_enc_jitter_en.35206671734469163232261404613229750352458496365918128839158230004067819535899
    Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_enc_jitter_en.71630113765070863529268558999799685537680230770199877247762899691259268334985
    Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.47979561892796816450526233159315061200690170262397040438646894459128991358072
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.61732573637833464114678001843551557684456582319458067066517549851815730950861
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.4778668782954296192521404512983562062167384125941089365005879380292253446547
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_mode_kmac_jitter_en.82245240031161027679382376035387167100556671309438680139222440192042414817567
    Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.79638587840701451290380972300048923116612807134438651219627493869833282508439
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en_reduced_freq.64944123672523947594476929987311237228546761980150970670558177920516999248277
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 14 failures:

Test chip_sw_rstmgr_alert_info has 3 failures.

0.chip_sw_rstmgr_alert_info.95190027974636237397993608182027064017465659597582102348081109443965612743683
Line 445, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30018.662354 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30018.662354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_alert_info.110121051712107247819914987646856281670303241969255039194079412380279635733889
Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30015.695265 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30015.695265 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_rstmgr_cpu_info has 3 failures.

0.chip_sw_rstmgr_cpu_info.98277141214185532050740954617487838159437282660125366540504189029856890541403
Line 495, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20022.121195 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20022.121195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_cpu_info.26572182036590817565710434070750776938959744329221248107203948168271066851264
Line 451, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20014.899895 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20014.899895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_irq has 3 failures.

0.chip_sw_aon_timer_irq.50765682107091867177277753791329888763423072516191127706669967066471324707795
Line 447, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18019.915645 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18019.915645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_irq.99075434162948459830497747692452260594125286631189416974375828325237481219226
Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18015.990519 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.990519 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 5 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.33800212759772295086313448571243642450018835048907033108899088050198844428931
Line 448, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18026.008176 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.008176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_sleep_wdog_sleep_pause.38751582341405069573641502776332595271003290972208611375285034527881773787571
Line 445, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18017.239123 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.239123 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
- Test chip_padctrl_attributes has 10 failures.
  - 0.chip_padctrl_attributes.57358630551526191744137082437368692423253141873228426930861320243682465416294
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.chip_padctrl_attributes.642314961448737438393986536609945364241514703755826644698866287303043160946
    Line 310, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.109278692324097152555968708244237316555059332271889370821223626872722508890746
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_bit_bash.92369110087374063349765046345622057538207400050583587833610320958566023543260
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.27457689013653006351796562111528984082607197451301074270998433876890033099822
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_aliasing.40958780470120808090668262372421121443360938420020384827624539484342483748040
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.100571283301338980460455211976532864490601916269397101514924812538541137067965
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_same_csr_outstanding.7171728217642010454004004082936894836578604536742287167838208577856243810697
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 9 failures:

Test chip_tl_errors has 9 failures.

3.chip_tl_errors.25104705259292662766401536610276495063120484955892665802634410652182321468718
Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_tl_errors/latest/run.log

      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3554.404000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3554.404000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.chip_tl_errors.41050150370153440346105576882202434952210845616729077466974068021019176915718
Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_tl_errors/latest/run.log

      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3925.177912 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3925.177912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 6 failures:

Test chip_sw_keymgr_dpe_key_derivation has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation.89044692972498940811293848433835002671554474492057755648633037249938819249397
Line 484, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 5792.248136 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (113855586432154523326028502399385391887892521314106835587696761126048293798227 [0xfbb7fa6ed7bbc3acd0bf4cffee2d902bb7110943fee251e26275a778fd994153] vs 4224767592382032366196545295362686699579115633799225472917568504330801831107 [0x957223b638dd9fb2f883f410e62b913653e78fbe53b86deb68b435f2beadcc3])
  UVM_INFO @ 5792.248136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation.66022568456851118733997327978965478934115662539801224517134946166589295721224
Line 473, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 7014.288696 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (76801199305978150723301222808011900187768711624218055619494013542752348972713 [0xa9cbf03875841686aa627b832b5d6e32d71d74e57a68cd2f5378a75b35e2a6a9] vs 111442786033056543824562523799091137095110919898363950058291627149540539475308 [0xf66261b2091a31061ad589a6582e8e1d2f2e52bbad730507e48a2965d5d3a56c])
  UVM_INFO @ 7014.288696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.66725667183163033924050658957775120801997651169260718979714411209950744184174
Line 484, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6669.922000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (4503769054486254083523109649825702422914710475229763159654932181987277529194 [0x9f50afec8217acac355e9206c0e82ff781e909fc18a502d10cd37aa2389e06a] vs 48221102453613006305903764305368189526075840634691015299887248655317077860286 [0x6a9c2d422381a0751d78d96c433e664ec99fdf26de21ed0e0e1e233aad4c1fbe])
  UVM_INFO @ 6669.922000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation_prod.102619195011869045604553255463051881563334510924190811636935033446856848868659
Line 472, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8187.046680 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (45829987976304786195868181173188943015479234972256400443479179179747793157265 [0x6552da9ce05bef4249fadb81f173d2080c864fc02afb3e1f5fb72bc90523bc91] vs 70043134815061881866342695054131487337212164549391957880230492899719712404054 [0x9adb0268b1ce8c86386ba38cfd5e3bdbd5be48f611d6fe1bef764e211e30f256])
  UVM_INFO @ 8187.046680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

Test chip_jtag_csr_rw has 3 failures.

0.chip_jtag_csr_rw.15851478154466690143380499246647979269224898085598105534201520157668081906795
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4973.339673 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h56faa6f8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h1  a_user: 'h248fb  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4973.339673 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_csr_rw.68432243047935711888416274896206215045403505925213400562490518617071459896132
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 5311.200879 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hd366052b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h0  a_user: 'h2692b  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5311.200879 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_jtag_mem_access has 3 failures.

0.chip_jtag_mem_access.91476301571898725884369098594615051026381423497379548284479560327103295471301
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3123.392758 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h9afe7b60  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h1  a_user: 'h24886  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3123.392758 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_mem_access.42973682566919851309576773626571936631672786756052325892089459195378567380103
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3273.095800 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hcd745199  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h1  a_user: 'h24899  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3273.095800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 5 failures:
- Test chip_sw_all_escalation_resets has 5 failures.
  - 26.chip_sw_all_escalation_resets.43042429237492740237857584134353645811388751235958098055310659744775250896784
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 12010.320001 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 53.chip_sw_all_escalation_resets.33230671146580295028655280299978438556132641912394843968762918747164539833429
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 12010.280001 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected *, got * has 4 failures:
- Test chip_sw_all_escalation_resets has 4 failures.
  - 3.chip_sw_all_escalation_resets.68034655195394960837981692783700891570650170439218985929014922459348655879805
    Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 4800.992840 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 4800.992840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 21.chip_sw_all_escalation_resets.54181978823026021740574569975429061865621262494619648848816341772923446473782
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 5059.198296 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 5059.198296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_example_rom has 3 failures.
  - 0.chip_sw_example_rom.25553620716177807685245822391653779379844598231591187118898796373627269341061
    Line 640, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_example_rom.106976822807134138406085142528311842314176642561519824096413290174274271684713
    Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.18849187057975122359163835959779159722740272833220551296715833197601727835508
    Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 6019.818360 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 6019.818360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.64959011657832069729561573023478212825372413949215462718266197341960676591948
    Line 455, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4584.089704 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4584.089704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:34)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceTwo, kDifToggleEnabled) returns * has 3 failures:
- Test chip_sw_soc_proxy_smoketest has 3 failures.
  - 0.chip_sw_soc_proxy_smoketest.33059422751865067206922748491529846931122126429199137292036747439637912384147
    Line 444, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 4031.859400 us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:34)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceTwo, kDifToggleEnabled) returns 3
  UVM_INFO @ 4031.859400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_soc_proxy_smoketest.47344718049252392282080931111331547825607602331127864757074053925233279537713
    Line 448, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 3908.443224 us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:34)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceTwo, kDifToggleEnabled) returns 3
  UVM_INFO @ 3908.443224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 3 failures:

Test chip_sw_soc_proxy_external_alerts has 3 failures.

0.chip_sw_soc_proxy_external_alerts.7569715916450393138246578951444838694538043406137262284911298873352893264665
Line 462, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 3176.429360 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3176.429360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_soc_proxy_external_alerts.39528813937501135486968866297784425945392104099242589161821402071695877436816
Line 440, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 4231.119970 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4231.119970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
- Test chip_sw_soc_proxy_external_wakeup has 3 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.74532863266305969729172393188275158663402593824283487648228659544975195609234
    Line 459, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4489.048440 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4489.048440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_soc_proxy_external_wakeup.27284401689843100052991772605426455032128260923925740497091115851702228492691
    Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4429.343276 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4429.343276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 3 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.74988753782860919033359400540018990801053581826146793614684902959627483180312
    Line 444, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5327.330452 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5327.330452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aon_timer_wdog_bite_reset.83205420347223611663301373880056984727026650845043082794944102639910906634248
    Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5974.758028 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5974.758028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.55818966296391637202055624626200574989637534888680746617860975693297823532629
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5453.666380 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5453.666380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rv_core_ibex_nmi_irq.5757280664347130692634918670712122169854636289651960596264035164263217236409
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6771.694260 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6771.694260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_kmac_app_rom has 3 failures.
  - 0.chip_sw_kmac_app_rom.108024197592268199069645956575820055463082132805251986035560830083805646166333
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_app_rom.15307731606704066359566614550430569015138218942588420176910709151093029642521
    Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 3 failures:
- Test chip_rv_dm_ndm_reset_req has 3 failures.
  - 0.chip_rv_dm_ndm_reset_req.77938889536532118758141911788577399975185210924258696497163924080500485310811
    Line 412, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14637.360676 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14637.360676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_rv_dm_ndm_reset_req.12876401842541829201398121790170807461784945466006894346377511961587686259875
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14745.998752 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14745.998752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 3 failures:

Test chip_sw_dma_abort has 3 failures.

0.chip_sw_dma_abort.106814071839162044241676243184550633924256332345312218454369801936440905971654
Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4543.904380 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4543.904380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_dma_abort.55179178246689889473413476677073381626964136191066300714103734315336530110701
Line 448, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 5664.793672 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5664.793672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36952) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures: