AES/MASKED Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	100.856us	1	1	100.00
V1	smoke	aes_smoke	7.000s	131.263us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	53.537us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	83.648us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	2.797ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	135.743us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	133.494us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	83.648us	20	20	100.00
		aes_csr_aliasing	6.000s	135.743us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	131.263us	50	50	100.00
		aes_config_error	8.000s	267.305us	50	50	100.00
		aes_stress	57.000s	3.732ms	50	50	100.00
V2	key_length	aes_smoke	7.000s	131.263us	50	50	100.00
		aes_config_error	8.000s	267.305us	50	50	100.00
		aes_stress	57.000s	3.732ms	50	50	100.00
V2	back2back	aes_stress	57.000s	3.732ms	50	50	100.00
		aes_b2b	21.000s	1.890ms	50	50	100.00
V2	backpressure	aes_stress	57.000s	3.732ms	50	50	100.00
V2	multi_message	aes_smoke	7.000s	131.263us	50	50	100.00
		aes_config_error	8.000s	267.305us	50	50	100.00
		aes_stress	57.000s	3.732ms	50	50	100.00
		aes_alert_reset	1.683m	6.841ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	421.268us	50	50	100.00
		aes_config_error	8.000s	267.305us	50	50	100.00
		aes_alert_reset	1.683m	6.841ms	50	50	100.00
V2	trigger_clear_test	aes_clear	20.000s	934.069us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	648.613us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.683m	6.841ms	50	50	100.00
V2	stress	aes_stress	57.000s	3.732ms	50	50	100.00
V2	sideload	aes_stress	57.000s	3.732ms	50	50	100.00
		aes_sideload	9.000s	229.007us	50	50	100.00
V2	deinitialization	aes_deinit	39.000s	2.601ms	50	50	100.00
V2	stress_all	aes_stress_all	58.000s	4.888ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	55.690us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	424.443us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	424.443us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	53.537us	5	5	100.00
		aes_csr_rw	5.000s	83.648us	20	20	100.00
		aes_csr_aliasing	6.000s	135.743us	5	5	100.00
		aes_same_csr_outstanding	6.000s	89.447us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	53.537us	5	5	100.00
		aes_csr_rw	5.000s	83.648us	20	20	100.00
		aes_csr_aliasing	6.000s	135.743us	5	5	100.00
		aes_same_csr_outstanding	6.000s	89.447us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	28.000s	5.581ms	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	951.801us	50	50	100.00
		aes_control_fi	51.000s	10.006ms	272	300	90.67
		aes_cipher_fi	46.000s	10.221ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	78.267us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	78.267us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	78.267us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	78.267us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	136.459us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.475ms	5	5	100.00
		aes_tl_intg_err	6.000s	190.869us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	190.869us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.683m	6.841ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	78.267us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	131.263us	50	50	100.00
		aes_stress	57.000s	3.732ms	50	50	100.00
		aes_alert_reset	1.683m	6.841ms	50	50	100.00
		aes_core_fi	17.000s	10.021ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	78.267us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	323.267us	50	50	100.00
		aes_stress	57.000s	3.732ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	57.000s	3.732ms	50	50	100.00
		aes_sideload	9.000s	229.007us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	323.267us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	323.267us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	323.267us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	323.267us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	323.267us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	57.000s	3.732ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	57.000s	3.732ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	951.801us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	951.801us	50	50	100.00
		aes_control_fi	51.000s	10.006ms	272	300	90.67
		aes_cipher_fi	46.000s	10.221ms	341	350	97.43
		aes_ctr_fi	6.000s	224.020us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	951.801us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	951.801us	50	50	100.00
		aes_control_fi	51.000s	10.006ms	272	300	90.67
		aes_cipher_fi	46.000s	10.221ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.221ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	951.801us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	951.801us	50	50	100.00
		aes_control_fi	51.000s	10.006ms	272	300	90.67
		aes_ctr_fi	6.000s	224.020us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	951.801us	50	50	100.00
		aes_control_fi	51.000s	10.006ms	272	300	90.67
		aes_cipher_fi	46.000s	10.221ms	341	350	97.43
		aes_ctr_fi	6.000s	224.020us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.683m	6.841ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	951.801us	50	50	100.00
		aes_control_fi	51.000s	10.006ms	272	300	90.67
		aes_cipher_fi	46.000s	10.221ms	341	350	97.43
		aes_ctr_fi	6.000s	224.020us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	951.801us	50	50	100.00
		aes_control_fi	51.000s	10.006ms	272	300	90.67
		aes_cipher_fi	46.000s	10.221ms	341	350	97.43
		aes_ctr_fi	6.000s	224.020us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	951.801us	50	50	100.00
		aes_control_fi	51.000s	10.006ms	272	300	90.67
		aes_ctr_fi	6.000s	224.020us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	951.801us	50	50	100.00
		aes_control_fi	51.000s	10.006ms	272	300	90.67
		aes_cipher_fi	46.000s	10.221ms	341	350	97.43
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	26.000s	3.024ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.39	98.60	96.45	99.44	95.66	97.99	97.78	99.11	97.79

Failure Buckets

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 18 failures:
- Test aes_control_fi has 18 failures.
  - 35.aes_control_fi.17720243612313872244584834452271813407127734305556472889896434736503448748951
    Line 133, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011871646 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011871646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 38.aes_control_fi.26979191843173387380125598337710199672744729667442165363179295373602614141065
    Line 145, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/38.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10047655800 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10047655800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
Job timed out after * minutes has 11 failures:
- Test aes_control_fi has 10 failures.
  - 16.aes_control_fi.85314642249550363218108672441282171522746673125361498058461503383128931409257
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 68.aes_control_fi.35880611829023733413002867283158614468520462396308494599997808415361367618386
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/68.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
- Test aes_cipher_fi has 1 failures.
  - 237.aes_cipher_fi.65448880857247706177838764391533314841703608261783104842793974768467436927422
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/237.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 58.aes_cipher_fi.26625348950307482954251508960013377915070151003143298682375392944656513834851
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/58.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10041384056 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10041384056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 113.aes_cipher_fi.42829925487485677684119139005888722219563170120765546098175210130679658547833
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/113.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10057852639 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10057852639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.49329709151606319668725316331511895101231505365819989388545843618917887241432
Line 181, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 246000931 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 246000931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.62031300873825653660204329268877226583071792860305070052505409706714494264289
Line 244, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 242319006 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 242319006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.40876682688854563171183622962784062500298895384432825784089448586942242310191
    Line 496, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1601084338 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1601084338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.101064803840890074340675743759801296435554544328022400493714466102705126927898
    Line 164, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  86387166 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  86387166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.91974988035846503905978970773594223708049332680300672676137187415312035044621
    Line 157, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 448294786 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 448294786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 69.aes_core_fi.12756585847854656275714933414411474625839316644664860122806084141546166030713
    Line 145, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/69.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021194104 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021194104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```