AES/UNMASKED Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	58.627us	1	1	100.00
V1	smoke	aes_smoke	7.000s	110.852us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	9.000s	124.868us	5	5	100.00
V1	csr_rw	aes_csr_rw	9.000s	54.888us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	127.750us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	10.000s	168.567us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	9.000s	126.195us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	9.000s	54.888us	20	20	100.00
		aes_csr_aliasing	10.000s	168.567us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	110.852us	50	50	100.00
		aes_config_error	11.000s	304.706us	50	50	100.00
		aes_stress	7.000s	77.040us	50	50	100.00
V2	key_length	aes_smoke	7.000s	110.852us	50	50	100.00
		aes_config_error	11.000s	304.706us	50	50	100.00
		aes_stress	7.000s	77.040us	50	50	100.00
V2	back2back	aes_stress	7.000s	77.040us	50	50	100.00
		aes_b2b	9.000s	180.338us	50	50	100.00
V2	backpressure	aes_stress	7.000s	77.040us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	110.852us	50	50	100.00
		aes_config_error	11.000s	304.706us	50	50	100.00
		aes_stress	7.000s	77.040us	50	50	100.00
		aes_alert_reset	7.000s	285.596us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	62.180us	50	50	100.00
		aes_config_error	11.000s	304.706us	50	50	100.00
		aes_alert_reset	7.000s	285.596us	50	50	100.00
V2	trigger_clear_test	aes_clear	8.000s	256.133us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	361.680us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	285.596us	50	50	100.00
V2	stress	aes_stress	7.000s	77.040us	50	50	100.00
V2	sideload	aes_stress	7.000s	77.040us	50	50	100.00
		aes_sideload	7.000s	144.382us	50	50	100.00
V2	deinitialization	aes_deinit	12.000s	162.291us	50	50	100.00
V2	stress_all	aes_stress_all	37.000s	1.711ms	9	10	90.00
V2	alert_test	aes_alert_test	6.000s	63.965us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	11.000s	506.533us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	11.000s	506.533us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	9.000s	124.868us	5	5	100.00
		aes_csr_rw	9.000s	54.888us	20	20	100.00
		aes_csr_aliasing	10.000s	168.567us	5	5	100.00
		aes_same_csr_outstanding	9.000s	148.515us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	9.000s	124.868us	5	5	100.00
		aes_csr_rw	9.000s	54.888us	20	20	100.00
		aes_csr_aliasing	10.000s	168.567us	5	5	100.00
		aes_same_csr_outstanding	9.000s	148.515us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	7.000s	136.878us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	551.216us	50	50	100.00
		aes_control_fi	29.000s	10.008ms	279	300	93.00
		aes_cipher_fi	40.000s	10.002ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	9.000s	85.787us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	9.000s	85.787us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	9.000s	85.787us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	9.000s	85.787us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	11.000s	273.326us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	3.763ms	5	5	100.00
		aes_tl_intg_err	10.000s	776.898us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	776.898us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	285.596us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	9.000s	85.787us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	110.852us	50	50	100.00
		aes_stress	7.000s	77.040us	50	50	100.00
		aes_alert_reset	7.000s	285.596us	50	50	100.00
		aes_core_fi	1.867m	10.021ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	9.000s	85.787us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	57.919us	50	50	100.00
		aes_stress	7.000s	77.040us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	77.040us	50	50	100.00
		aes_sideload	7.000s	144.382us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	57.919us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	57.919us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	57.919us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	57.919us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	57.919us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	77.040us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	77.040us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	551.216us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	551.216us	50	50	100.00
		aes_control_fi	29.000s	10.008ms	279	300	93.00
		aes_cipher_fi	40.000s	10.002ms	329	350	94.00
		aes_ctr_fi	6.000s	73.653us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	551.216us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	551.216us	50	50	100.00
		aes_control_fi	29.000s	10.008ms	279	300	93.00
		aes_cipher_fi	40.000s	10.002ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	40.000s	10.002ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	551.216us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	551.216us	50	50	100.00
		aes_control_fi	29.000s	10.008ms	279	300	93.00
		aes_ctr_fi	6.000s	73.653us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	551.216us	50	50	100.00
		aes_control_fi	29.000s	10.008ms	279	300	93.00
		aes_cipher_fi	40.000s	10.002ms	329	350	94.00
		aes_ctr_fi	6.000s	73.653us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	285.596us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	551.216us	50	50	100.00
		aes_control_fi	29.000s	10.008ms	279	300	93.00
		aes_cipher_fi	40.000s	10.002ms	329	350	94.00
		aes_ctr_fi	6.000s	73.653us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	551.216us	50	50	100.00
		aes_control_fi	29.000s	10.008ms	279	300	93.00
		aes_cipher_fi	40.000s	10.002ms	329	350	94.00
		aes_ctr_fi	6.000s	73.653us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	551.216us	50	50	100.00
		aes_control_fi	29.000s	10.008ms	279	300	93.00
		aes_ctr_fi	6.000s	73.653us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	551.216us	50	50	100.00
		aes_control_fi	29.000s	10.008ms	279	300	93.00
		aes_cipher_fi	40.000s	10.002ms	329	350	94.00
V2S		TOTAL			940	985	95.43
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	22.000s	6.291ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1546	1602	96.50

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.28	97.62	94.63	98.78	93.51	98.07	91.11	98.85	98.59

Failure Buckets

Job timed out after * minutes has 28 failures:
- Test aes_control_fi has 17 failures.
  - 3.aes_control_fi.110851645021202010173261323181115755482465116462319694401692067949635336452555
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 12.aes_control_fi.64631710193366646117098754122259611855711360874282697653429801985521832172486
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 15 more failures.
- Test aes_cipher_fi has 11 failures.
  - 10.aes_cipher_fi.81068377318332809339668470235613468101606862466180240099894498039876748722962
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 19.aes_cipher_fi.4410858867573155189723980161507976960368700652177449794260491680536913058563
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 21.aes_cipher_fi.59710319474888041170168586291924695132934352367740373803508796198149099268297
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007117493 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007117493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 100.aes_cipher_fi.88786943297902989002410206532537969039889440613555351777665242056682620842517
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/100.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007959705 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007959705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.84907068816203505236770904565698906072304728193448028169984716906207482952547
Line 1241, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 714304006 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 714304006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.5884881623542813130495781843277224200278123263371252490548459072893747712268
Line 908, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3218251440 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3218251440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 9.aes_control_fi.73506009186143706771320480666928704100773636445389188484944194574157750269744
    Line 147, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10022935856 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022935856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 49.aes_control_fi.70531682255433683128102962251628960033152576745913972803017970706058099458579
    Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008484849 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008484849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_stress_all has 1 failures.

6.aes_stress_all.46976869172022301134878322922864160393597199859845274632872288390773122595964
Line 28872, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 378711256 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 378671256 PS)
  UVM_ERROR @ 378711256 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 378711256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_stress_all_with_rand_reset has 1 failures.

7.aes_stress_all_with_rand_reset.30210255801128365959343013563092801249740031972355116000835209683798190282014
Line 486, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 136227639 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 136217222 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 136227639 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 136217222 PS)
  UVM_ERROR @ 136227639 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.80615082602122302593532966842735785397765041918343239249689179986440603676776
    Line 168, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2227738265 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2227738265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.46702171671112449249997982064645148468240016081715614853373240527843201290845
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  51212748 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  51212748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 26.aes_core_fi.90379773762037936558726858475805011229259750008658993800627815888741254583425
    Line 145, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/26.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017582550 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017582550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 48.aes_core_fi.115747591731776806802936862047338254853701266376459705785065401967770013601481
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/48.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021047960 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x55888d84, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10021047960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 60.aes_core_fi.79154607950052410179555810498647766774703471191026351678655020548600966341543
    Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/60.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10031475886 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xdf31f684, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10031475886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```