AON_TIMER Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	3.250s	678.025us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	3.440s	875.175us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.800s	432.208us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	16.100s	13.663ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	3.070s	391.111us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.450s	279.300us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.800s	432.208us	20	20	100.00
		aon_timer_csr_aliasing	3.070s	391.111us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	2.480s	454.290us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	2.700s	360.761us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	1.347m	62.009ms	15	15	100.00
V2	jump	aon_timer_jump	3.860s	695.346us	5	5	100.00
V2	stress_all	aon_timer_stress_all	1.994m	164.997ms	15	15	100.00
V2	alert_test	aon_timer_alert_test	3.320s	471.063us	50	50	100.00
V2	intr_test	aon_timer_intr_test	2.610s	485.336us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.680s	498.236us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.680s	498.236us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	3.440s	875.175us	5	5	100.00
		aon_timer_csr_rw	2.800s	432.208us	20	20	100.00
		aon_timer_csr_aliasing	3.070s	391.111us	5	5	100.00
		aon_timer_same_csr_outstanding	5.810s	2.310ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	3.440s	875.175us	5	5	100.00
		aon_timer_csr_rw	2.800s	432.208us	20	20	100.00
		aon_timer_csr_aliasing	3.070s	391.111us	5	5	100.00
		aon_timer_same_csr_outstanding	5.810s	2.310ms	20	20	100.00
V2		TOTAL			175	175	100.00
V2S	tl_intg_err	aon_timer_sec_cm	8.770s	4.513ms	5	5	100.00
		aon_timer_tl_intg_err	13.870s	8.774ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.870s	8.774ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	max_threshold	aon_timer_smoke_max_thold	2.480s	598.399us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	3.080s	653.106us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	5.950s	3.795ms	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	3.260s	554.358us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	18.840s	4.224ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	40.250s	21.202ms	15	15	100.00
V3		TOTAL			45	45	100.00
		TOTAL			315	315	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00