CSRNG Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	68.337us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	47.232us	5	5	100.00
V1	csr_rw	csrng_csr_rw	7.000s	96.449us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	31.000s	1.649ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	13.000s	309.537us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	103.879us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	7.000s	96.449us	20	20	100.00
		csrng_csr_aliasing	13.000s	309.537us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	26.000s	1.933ms	198	200	99.00
V2	alerts	csrng_alert	1.167m	4.686ms	500	500	100.00
V2	err	csrng_err	10.000s	20.771us	499	500	99.80
V2	cmds	csrng_cmds	6.583m	29.593ms	50	50	100.00
V2	life cycle	csrng_cmds	6.583m	29.593ms	50	50	100.00
V2	stress_all	csrng_stress_all	25.383m	129.421ms	49	50	98.00
V2	intr_test	csrng_intr_test	7.000s	113.750us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	47.292us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	11.000s	98.063us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	11.000s	98.063us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	47.232us	5	5	100.00
		csrng_csr_rw	7.000s	96.449us	20	20	100.00
		csrng_csr_aliasing	13.000s	309.537us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	404.083us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	47.232us	5	5	100.00
		csrng_csr_rw	7.000s	96.449us	20	20	100.00
		csrng_csr_aliasing	13.000s	309.537us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	404.083us	20	20	100.00
V2		TOTAL			1436	1440	99.72
V2S	tl_intg_err	csrng_sec_cm	9.000s	94.090us	5	5	100.00
		csrng_tl_intg_err	27.000s	445.602us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	139.774us	50	50	100.00
		csrng_csr_rw	7.000s	96.449us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.167m	4.686ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.383m	129.421ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
		csrng_sec_cm	9.000s	94.090us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
		csrng_sec_cm	9.000s	94.090us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
		csrng_sec_cm	9.000s	94.090us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
		csrng_sec_cm	9.000s	94.090us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
		csrng_sec_cm	9.000s	94.090us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
		csrng_sec_cm	9.000s	94.090us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
		csrng_sec_cm	9.000s	94.090us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.167m	4.686ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.383m	129.421ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.167m	4.686ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	27.000s	445.602us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
		csrng_sec_cm	9.000s	94.090us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
		csrng_sec_cm	9.000s	94.090us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	26.000s	1.933ms	198	200	99.00
		csrng_err	10.000s	20.771us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.883m	6.664ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1616	1630	99.14

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.76	98.63	96.68	99.97	97.42	92.15	100.00	97.36	90.46

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.14033201320568531087306768748104990518423030251029604110654435446263433737882
    Line 100, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 843752739 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 843752739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.csrng_stress_all_with_rand_reset.52142463803169437305196724287246111645384656373023192167269109244811736502376
    Line 109, in log /nightly/runs/scratch/master/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 977077979 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 977077979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 3 failures:

Test csrng_stress_all_with_rand_reset has 3 failures.

1.csrng_stress_all_with_rand_reset.33058546139887590152905227096216018169330697551728259029985636856774525401104
Line 104, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   5422566 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @   5422566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.csrng_stress_all_with_rand_reset.47440860721031271328365193856551647622928272828072500769531626848011840843600
Line 104, in log /nightly/runs/scratch/master/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  15178462 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  15178462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 2 failures:

Test csrng_intr has 2 failures.

128.csrng_intr.65425734687536025170000717454388343707659940923553241281602854492325709329441
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/128.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 180574721 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 180574721 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 180574721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

138.csrng_intr.47248356735161447386625953996483439820962029608876184691596936822985725036037
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/138.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 456282022 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 456282022 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 456282022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 31.csrng_stress_all.85664711707699433443349330737059263995030520625472531130388502876690412735053
    Line 137, in log /nightly/runs/scratch/master/csrng-sim-xcelium/31.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 536870683 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 536870683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 183.csrng_err.113060729115816870746166939527184484714631884665216435271624162683615831217649
    Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/183.csrng_err/latest/run.log
```
  UVM_ERROR @  11179366 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  11179366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```