DMA Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	11.000s	868.505us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	11.000s	600.878us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	12.000s	2.266ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	20.831us	5	5	100.00
V1	csr_rw	dma_csr_rw	5.000s	146.178us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	15.000s	1.534ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	313.388us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	6.000s	128.863us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	146.178us	20	20	100.00
		dma_csr_aliasing	9.000s	313.388us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.950m	5.797ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	40.700m	244.252ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	18.567m	107.944ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	50.000m	945.079ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	40.700m	244.252ms	3	3	100.00
V2	dma_abort	dma_abort	16.000s	1.881ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	2.033m	15.766ms	3	3	100.00
V2	intr_test	dma_intr_test	5.000s	38.152us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	592.787us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	592.787us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	20.831us	5	5	100.00
		dma_csr_rw	5.000s	146.178us	20	20	100.00
		dma_csr_aliasing	9.000s	313.388us	5	5	100.00
		dma_same_csr_outstanding	6.000s	55.745us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	20.831us	5	5	100.00
		dma_csr_rw	5.000s	146.178us	20	20	100.00
		dma_csr_aliasing	9.000s	313.388us	5	5	100.00
		dma_same_csr_outstanding	6.000s	55.745us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	24.000s	146.775us	5	5	100.00
		dma_generic_stress	50.000m	945.079ms	5	5	100.00
		dma_handshake_stress	40.700m	244.252ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	224.255us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.117m	6.872ms	5	5	100.00
		dma_longer_transfer	12.000s	1.587ms	5	5	100.00
		TOTAL			304	304	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
76.00	96.97	95.19	96.93	95.97	82.72	82.76	97.77	42.16