EDN Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.600s 29.162us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.330s 45.330us 5 5 100.00
V1 csr_rw edn_csr_rw 2.330s 12.568us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.730s 1.036ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.630s 42.190us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.780s 35.016us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.330s 12.568us 20 20 100.00
edn_csr_aliasing 2.630s 42.190us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.310s 399.092us 300 300 100.00
V2 csrng_commands edn_genbits 5.310s 399.092us 300 300 100.00
V2 genbits edn_genbits 5.310s 399.092us 300 300 100.00
V2 interrupts edn_intr 2.600s 20.933us 50 50 100.00
V2 alerts edn_alert 3.290s 51.650us 200 200 100.00
V2 errs edn_err 3.110s 30.061us 100 100 100.00
V2 disable edn_disable 2.540s 14.179us 50 50 100.00
edn_disable_auto_req_mode 2.930s 58.312us 50 50 100.00
V2 stress_all edn_stress_all 9.230s 367.758us 50 50 100.00
V2 intr_test edn_intr_test 2.240s 16.824us 50 50 100.00
V2 alert_test edn_alert_test 3.000s 64.553us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.870s 262.533us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.870s 262.533us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.330s 45.330us 5 5 100.00
edn_csr_rw 2.330s 12.568us 20 20 100.00
edn_csr_aliasing 2.630s 42.190us 5 5 100.00
edn_same_csr_outstanding 2.600s 126.909us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.330s 45.330us 5 5 100.00
edn_csr_rw 2.330s 12.568us 20 20 100.00
edn_csr_aliasing 2.630s 42.190us 5 5 100.00
edn_same_csr_outstanding 2.600s 126.909us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.450s 2.001ms 5 5 100.00
edn_tl_intg_err 4.140s 1.165ms 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.340s 15.108us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 3.290s 51.650us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.450s 2.001ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.450s 2.001ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.450s 2.001ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.450s 2.001ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 3.290s 51.650us 200 200 100.00
edn_sec_cm 9.450s 2.001ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 3.290s 51.650us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.140s 1.165ms 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.488m 20.453ms 25 50 50.00
V3 TOTAL 25 50 50.00
TOTAL 1105 1130 97.79

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.48 98.32 94.23 97.02 89.53 96.33 99.78 93.13

Failure Buckets