HMAC Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	14.660s	745.400us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.490s	80.689us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.520s	86.158us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.770s	5.260ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	10.230s	453.408us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	11.267m	248.408ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.520s	86.158us	20	20	100.00
		hmac_csr_aliasing	10.230s	453.408us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.872m	56.494ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.661m	3.411ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.094m	45.316ms	30	30	100.00
		hmac_test_sha384_vectors	8.488m	12.640ms	75	75	100.00
		hmac_test_sha512_vectors	9.406m	15.456ms	75	75	100.00
		hmac_test_hmac256_vectors	15.310s	334.863us	50	50	100.00
		hmac_test_hmac384_vectors	18.030s	375.201us	60	60	100.00
		hmac_test_hmac512_vectors	22.190s	2.725ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	37.720s	718.574us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	24.005m	30.561ms	10	10	100.00
V2	error	hmac_error	1.927m	4.504ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.950m	2.678ms	10	10	100.00
V2	save_and_restore	hmac_smoke	14.660s	745.400us	10	10	100.00
		hmac_long_msg	1.872m	56.494ms	10	10	100.00
		hmac_back_pressure	1.661m	3.411ms	25	25	100.00
		hmac_datapath_stress	24.005m	30.561ms	10	10	100.00
		hmac_burst_wr	37.720s	718.574us	50	50	100.00
		hmac_stress_all	38.389m	1.135s	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	14.660s	745.400us	10	10	100.00
		hmac_long_msg	1.872m	56.494ms	10	10	100.00
		hmac_back_pressure	1.661m	3.411ms	25	25	100.00
		hmac_datapath_stress	24.005m	30.561ms	10	10	100.00
		hmac_wipe_secret	1.950m	2.678ms	10	10	100.00
		hmac_test_sha256_vectors	4.094m	45.316ms	30	30	100.00
		hmac_test_sha384_vectors	8.488m	12.640ms	75	75	100.00
		hmac_test_sha512_vectors	9.406m	15.456ms	75	75	100.00
		hmac_test_hmac256_vectors	15.310s	334.863us	50	50	100.00
		hmac_test_hmac384_vectors	18.030s	375.201us	60	60	100.00
		hmac_test_hmac512_vectors	22.190s	2.725ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	14.660s	745.400us	10	10	100.00
		hmac_long_msg	1.872m	56.494ms	10	10	100.00
		hmac_back_pressure	1.661m	3.411ms	25	25	100.00
		hmac_datapath_stress	24.005m	30.561ms	10	10	100.00
		hmac_burst_wr	37.720s	718.574us	50	50	100.00
		hmac_error	1.927m	4.504ms	10	10	100.00
		hmac_wipe_secret	1.950m	2.678ms	10	10	100.00
		hmac_test_sha256_vectors	4.094m	45.316ms	30	30	100.00
		hmac_test_sha384_vectors	8.488m	12.640ms	75	75	100.00
		hmac_test_sha512_vectors	9.406m	15.456ms	75	75	100.00
		hmac_test_hmac256_vectors	15.310s	334.863us	50	50	100.00
		hmac_test_hmac384_vectors	18.030s	375.201us	60	60	100.00
		hmac_test_hmac512_vectors	22.190s	2.725ms	75	75	100.00
		hmac_stress_all	38.389m	1.135s	50	50	100.00
V2	stress_all	hmac_stress_all	38.389m	1.135s	50	50	100.00
V2	alert_test	hmac_alert_test	2.110s	12.104us	50	50	100.00
V2	intr_test	hmac_intr_test	2.130s	19.124us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.990s	902.504us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.990s	902.504us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.490s	80.689us	5	5	100.00
		hmac_csr_rw	2.520s	86.158us	20	20	100.00
		hmac_csr_aliasing	10.230s	453.408us	5	5	100.00
		hmac_same_csr_outstanding	3.900s	122.122us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.490s	80.689us	5	5	100.00
		hmac_csr_rw	2.520s	86.158us	20	20	100.00
		hmac_csr_aliasing	10.230s	453.408us	5	5	100.00
		hmac_same_csr_outstanding	3.900s	122.122us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.650s	174.975us	5	5	100.00
		hmac_tl_intg_err	5.990s	1.171ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.990s	1.171ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	14.660s	745.400us	10	10	100.00
V3	stress_reset	hmac_stress_reset	7.260s	427.252us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	7.898m	57.856ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.440s	14.811us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.67	100.00	97.31	100.00	97.06	100.00	100.00	47.30