I2C Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.416m	2.092ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	34.120s	1.244ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.210s	32.663us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.280s	22.961us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	6.900s	2.586ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.560s	187.166us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.820s	28.228us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.280s	22.961us	20	20	100.00
		i2c_csr_aliasing	3.560s	187.166us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	25.314m	600.000ms	49	50	98.00
V2	host_stress_all	i2c_host_stress_all	51.896m	66.813ms	14	50	28.00
V2	host_maxperf	i2c_host_perf	43.566m	49.961ms	50	50	100.00
V2	host_override	i2c_host_override	2.230s	52.690us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.726m	5.445ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.325m	10.257ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.870s	526.814us	50	50	100.00
		i2c_host_fifo_fmt_empty	27.480s	592.940us	50	50	100.00
		i2c_host_fifo_reset_rx	12.540s	218.566us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	4.128m	16.996ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	45.960s	995.207us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	8.920s	157.219us	22	50	44.00
V2	target_glitch	i2c_target_glitch	7.190s	3.417ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	20.495m	64.255ms	48	50	96.00
V2	target_maxperf	i2c_target_perf	9.260s	3.548ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.127m	1.832ms	50	50	100.00
		i2c_target_intr_smoke	11.000s	4.640ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.510s	261.817us	50	50	100.00
		i2c_target_fifo_reset_tx	3.550s	715.720us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	25.356m	71.781ms	50	50	100.00
		i2c_target_stress_rd	1.127m	1.832ms	50	50	100.00
		i2c_target_intr_stress_wr	4.877m	17.002ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	11.190s	6.576ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.346m	2.103ms	47	50	94.00
V2	bad_address	i2c_target_bad_addr	9.780s	2.975ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	44.180s	10.077ms	24	50	48.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.010s	794.284us	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.390s	384.816us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	43.566m	49.961ms	50	50	100.00
		i2c_host_perf_precise	6.242m	24.482ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	45.960s	995.207us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	11.240s	907.839us	50	50	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.300s	10.197ms	50	50	100.00
		i2c_target_nack_acqfull_addr	5.190s	2.379ms	50	50	100.00
		i2c_target_nack_txstretch	3.460s	284.631us	32	50	64.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	22.780s	2.934ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.690s	673.900us	50	50	100.00
V2	alert_test	i2c_alert_test	2.190s	19.144us	50	50	100.00
V2	intr_test	i2c_intr_test	2.230s	22.676us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.970s	825.426us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.970s	825.426us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.210s	32.663us	5	5	100.00
		i2c_csr_rw	2.280s	22.961us	20	20	100.00
		i2c_csr_aliasing	3.560s	187.166us	5	5	100.00
		i2c_same_csr_outstanding	2.720s	716.489us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.210s	32.663us	5	5	100.00
		i2c_csr_rw	2.280s	22.961us	20	20	100.00
		i2c_csr_aliasing	3.560s	187.166us	5	5	100.00
		i2c_same_csr_outstanding	2.720s	716.489us	20	20	100.00
V2		TOTAL			1677	1792	93.58
V2S	tl_intg_err	i2c_tl_intg_err	3.970s	458.418us	20	20	100.00
		i2c_sec_cm	2.630s	128.630us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.970s	458.418us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	52.460s	4.144ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	4.700s	1.363ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	55.450s	10.957ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1857	2042	90.94

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.04	97.32	89.70	74.17	72.02	94.25	98.52	90.27

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 42 failures:

Test i2c_host_stress_all has 27 failures.

0.i2c_host_stress_all.100981172403646425809501385872891888143112070170328318525545855246942104249202
Line 174, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 19065135687 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4101988

6.i2c_host_stress_all.84069717553147234025733910805081757605167970394366362800035771724167156320039
Line 197, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 20198561947 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5691444

... and 25 more failures.

Test i2c_host_mode_toggle has 15 failures.

0.i2c_host_mode_toggle.33756038728694628115541958686556972241311678239170467055991515467710906833827
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 263673075 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @34053

3.i2c_host_mode_toggle.89490593335438230060632449396375650004595220957827924019728602656850479056074
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 716341777 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @22777

... and 13 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
- Test i2c_target_unexp_stop has 30 failures.
  - 0.i2c_target_unexp_stop.18334983160585470054936387771370351853416193422428891189646157850234281705801
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1364628745 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 156 [0x9c])
  UVM_INFO @ 1364628745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_unexp_stop.95432032873607616462547048102668511433391993087390562206559797389293591457163
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 172353963 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 68 [0x44])
  UVM_INFO @ 172353963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 28 more failures.
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 1.i2c_target_stress_all_with_rand_reset.92183831310492910729457304701571064705685641755485896720115835622762441696978
    Line 191, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10957361785 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 43 [0x2b])
  UVM_INFO @ 10957361785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_stress_all_with_rand_reset.62118509252513227378689754213698883307923260876695043432564844202503891144171
    Line 146, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2268482807 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 41 [0x29])
  UVM_INFO @ 2268482807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
- Test i2c_target_hrst has 26 failures.
  - 2.i2c_target_hrst.5882574793495740862793077088974336665176538247665260834242676973062773346120
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10058620054 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10058620054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_hrst.60843271663518900060952160096433441130285129165052809811410737529053031099441
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10028682287 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10028682287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 24 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 18 failures:
- Test i2c_target_nack_txstretch has 18 failures.
  - 3.i2c_target_nack_txstretch.16472371639301855552849087779151013725133547584032581958972720875467158382955
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 169818467 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 169818467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.i2c_target_nack_txstretch.31604463180447204924578905909938604029622047495612367759704712469186461250973
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 205957485 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 205957485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.108795177490232453721751571823027175730296772474495308087806271245839253613461
Line 105, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1783245044 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1783245044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.59447370177187648186790440419692908322655586753219275868547657525308567153763
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 150757442 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 150757442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

0.i2c_target_stress_all_with_rand_reset.88553147646670360061577696278973880146846493377981646764315811799568055514919
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 380715933 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 380715933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.59052451421112183887571388275512975394363898713718156299346503250103256192686
Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 309094014 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 309094014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 15 failures:
- Test i2c_target_unexp_stop has 15 failures.
  - 1.i2c_target_unexp_stop.13668061725289369640158744886042825874593554362595793250169654158533527209177
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  70334725 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  70334725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.87709709893477461522097593147949516216826893824605635666766023138520320033494
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  58823146 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  58823146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 9 failures:

Test i2c_host_mode_toggle has 9 failures.

5.i2c_host_mode_toggle.108109799259495660694769498938073943177139065750240134054152113356647117562032
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 236573446 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

8.i2c_host_mode_toggle.28300077909212342751143793740064021947935777781770519133492839910162925493386
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  44577082 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 7 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:

Test i2c_host_stress_all has 5 failures.

3.i2c_host_stress_all.108799398017402665423471711682651222872156956048718434615835583819765841284652
Line 185, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 15590167682 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4961938

24.i2c_host_stress_all.21356750673252962196970979581854457067023943215114808572246105642914471300471
Line 424, in log /nightly/runs/scratch/master/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 59054250313 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2927820

... and 3 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:

Test i2c_target_unexp_stop has 5 failures.

8.i2c_target_unexp_stop.111742019409462640090097953068170945528198994329751773593294909544202541452317
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 298957386 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 298957386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.i2c_target_unexp_stop.86580112226883839246982447689314740618150688947913624847601858132981725387612
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/26.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 123009682 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 123009682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
- Test i2c_host_mode_toggle has 4 failures.
  - 1.i2c_host_mode_toggle.109659645825356776987960824015864389015376123813811473244882982293901620334873
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  25120759 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x28c31a94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  25120759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_host_mode_toggle.27219398057773615021539533573338470090131315076473750772679710856363062397112
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 208218857 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xf09e14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 208218857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 3 failures:
- Test i2c_target_stretch has 3 failures.
  - 17.i2c_target_stretch.103751239560536087605247323085383302668295779921838389506087294546332914986047
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/17.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10041433989 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10041433989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 21.i2c_target_stretch.50190426683788965427567435410667164503342554185622604637477897672323795190077
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/21.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10043638900 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10043638900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
Job timed out after * minutes has 2 failures:
- Test i2c_host_stress_all has 2 failures.
  - 7.i2c_host_stress_all.100287493629820890508551897499847985788350153857450353550244570834007052340654
    Log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 10.i2c_host_stress_all.93679948780398834842879050775240775767577394252394900707265704847923265152583
    Log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test i2c_host_stress_all has 1 failures.
  - 12.i2c_host_stress_all.80420438941655095330826068430152034539229893280495595242515663571616554997939
    Line 295, in log /nightly/runs/scratch/master/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_host_error_intr has 1 failures.
  - 29.i2c_host_error_intr.114127117989269972225527045046832301914893923690381233969512621687997978606326
    Line 119, in log /nightly/runs/scratch/master/i2c-sim-vcs/29.i2c_host_error_intr/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
- Test i2c_target_stress_all has 2 failures.
  - 31.i2c_target_stress_all.49330413589338423461479245445732350321207324002347757785761406867549558066658
    Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/31.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 39974682399 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 39974682399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 39.i2c_target_stress_all.91371572948927458965197670951521666735898328718045389887525303026581894328427
    Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/39.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 45640234247 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 45640234247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 7.i2c_target_stress_all_with_rand_reset.33320411990267396947247706531013803724845764518095019697150876921535413328048
    Line 116, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 687122672 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
  UVM_INFO @ 687122672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 16.i2c_target_fifo_watermarks_tx.85252317673309120697840934863271563272466419775375333122953921536902093350455
    Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 28.i2c_host_stress_all.53189598310270933590424033277816900386609232737003701262630992797636301712771
    Line 128, in log /nightly/runs/scratch/master/i2c-sim-vcs/28.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 39556113165 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```