KEYMGR Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	31.850s	1.485ms	50	50	100.00
V1	random	keymgr_random	35.450s	1.948ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.560s	37.712us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.860s	47.783us	16	20	80.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.520s	5.769ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	14.570s	2.046ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.110s	110.116us	12	20	60.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.860s	47.783us	16	20	80.00
		keymgr_csr_aliasing	14.570s	2.046ms	5	5	100.00
V1		TOTAL			143	155	92.26
V2	cfgen_during_op	keymgr_cfg_regwen	1.476m	2.318ms	50	50	100.00
V2	sideload	keymgr_sideload	56.020s	6.540ms	50	50	100.00
		keymgr_sideload_kmac	30.040s	4.742ms	50	50	100.00
		keymgr_sideload_aes	27.090s	1.309ms	50	50	100.00
		keymgr_sideload_otbn	35.970s	2.235ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	14.550s	1.608ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.310s	788.501us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.560s	244.784us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	48.210s	2.471ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	54.420s	4.234ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	13.390s	1.541ms	50	50	100.00
V2	stress_all	keymgr_stress_all	8.429m	38.122ms	46	50	92.00
V2	intr_test	keymgr_intr_test	2.350s	18.142us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.480s	13.208us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.110s	143.911us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.110s	143.911us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.560s	37.712us	5	5	100.00
		keymgr_csr_rw	2.860s	47.783us	16	20	80.00
		keymgr_csr_aliasing	14.570s	2.046ms	5	5	100.00
		keymgr_same_csr_outstanding	4.510s	385.462us	14	20	70.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.560s	37.712us	5	5	100.00
		keymgr_csr_rw	2.860s	47.783us	16	20	80.00
		keymgr_csr_aliasing	14.570s	2.046ms	5	5	100.00
		keymgr_same_csr_outstanding	4.510s	385.462us	14	20	70.00
V2		TOTAL			729	740	98.51
V2S	sec_cm_additional_check	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
		keymgr_tl_intg_err	8.240s	1.067ms	17	20	85.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.380s	699.734us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.380s	699.734us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.380s	699.734us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.380s	699.734us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.140s	1.637ms	8	20	40.00
V2S	prim_count_check	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.240s	1.067ms	17	20	85.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.380s	699.734us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.476m	2.318ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	35.450s	1.948ms	50	50	100.00
		keymgr_csr_rw	2.860s	47.783us	16	20	80.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	35.450s	1.948ms	50	50	100.00
		keymgr_csr_rw	2.860s	47.783us	16	20	80.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	35.450s	1.948ms	50	50	100.00
		keymgr_csr_rw	2.860s	47.783us	16	20	80.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.310s	788.501us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	54.420s	4.234ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	54.420s	4.234ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	35.450s	1.948ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	20.310s	1.161ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	12.190s	876.935us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.310s	788.501us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	12.190s	876.935us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	12.190s	876.935us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	12.190s	876.935us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.910s	2.889ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	12.190s	876.935us	50	50	100.00
V2S		TOTAL			150	165	90.91
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	22.040s	508.740us	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1049	1110	94.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.10	98.03	98.57	100.00	99.01	98.63	91.18

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 33 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 12 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.7597607161978030023207928549844391457740526742279118695865845493388110388818
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @   9964222 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @   9964222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_shadow_reg_errors_with_csr_rw.14442127432894757136594526732552648743174645329618759328975082361864042771304
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @  25209440 ps: (keymgr_csr_assert_fpv.sv:396) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @  25209440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test keymgr_csr_rw has 4 failures.

1.keymgr_csr_rw.23509542116446636827462714649927876861929107251106700290356039411923749667793
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @  15514796 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @  15514796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.keymgr_csr_rw.46028978172317514318410520116675400172222539282807630832565204578706620378532
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/8.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @  17304726 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @  17304726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test keymgr_same_csr_outstanding has 6 failures.

1.keymgr_same_csr_outstanding.13180943210806422407785628964719512494427343676826235560296387528146051135700
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @  32690692 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @  32690692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_same_csr_outstanding.37341835038048301839921897009097301790852648231093878261231389251541856911623
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @ 123582863 ps: (keymgr_csr_assert_fpv.sv:446) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @ 123582863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_csr_mem_rw_with_rand_reset has 8 failures.

2.keymgr_csr_mem_rw_with_rand_reset.21250561577546996231347219345252856300518105386564152913945625425736232769751
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @   4461607 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @   4461607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_csr_mem_rw_with_rand_reset.81934352135073056016301484681181238568931301336069971842097796540204669262118
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @  67171848 ps: (keymgr_csr_assert_fpv.sv:446) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @  67171848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_tl_intg_err has 3 failures.

3.keymgr_tl_intg_err.44299508256882223923158002107099457396247583250601893473031319315580930195367
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @  38220262 ps: (keymgr_csr_assert_fpv.sv:396) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @  38220262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_tl_intg_err.23766548942507560963871051481067684393035193716176182004979166497899371742057
Line 104, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @ 164387624 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @ 164387624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test keymgr_stress_all_with_rand_reset has 21 failures.
  - 3.keymgr_stress_all_with_rand_reset.100500078669906190169541945821979393773751797997103606519436851529647309567551
    Line 627, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 516108700 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 516108700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.keymgr_stress_all_with_rand_reset.8838874196565783450693150819466016386404252000174100120976705643502014645306
    Line 918, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 255958950 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 255958950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.

UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

Test keymgr_stress_all has 3 failures.

0.keymgr_stress_all.93462943456927086702498979001588111871374268840582074597542378600751967789161
Line 2959, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 1537117782 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 1537117782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.keymgr_stress_all.89240530012138754094184206088835106132642121981786385316033059072873724164071
Line 272, in log /nightly/runs/scratch/master/keymgr-sim-vcs/28.keymgr_stress_all/latest/run.log

  UVM_ERROR @  63791737 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  63791737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_sw_invalid_input has 1 failures.

24.keymgr_sw_invalid_input.68302241166888599023024434374309925569986818301533424897016416311794273390523
Line 269, in log /nightly/runs/scratch/master/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest/run.log

  UVM_ERROR @  28926853 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  28926853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 26.keymgr_stress_all_with_rand_reset.56674959530873330899717841467933286832050830380286797663162900860087227608270
    Line 323, in log /nightly/runs/scratch/master/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 858567027 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 858567027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 43.keymgr_stress_all.42820502008045430278818707459575958993099739201355914425582695668038597331304
    Line 1148, in log /nightly/runs/scratch/master/keymgr-sim-vcs/43.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 430439157 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2394951691 [0x8ec0100b] vs 2394951691 [0x8ec0100b]) reg name: keymgr_reg_block.sw_share1_output_6
  UVM_INFO @ 430439157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:832) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 49.keymgr_stress_all_with_rand_reset.36804978362284971588493641275667286511649595355385957083809161105295621531989
    Line 91, in log /nightly/runs/scratch/master/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 477727801 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 477727801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```