KEYMGR_DPE Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	3.314m	54.430ms	50	50	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	2.420s	16.525us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	2.460s	130.024us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	16.880s	875.832us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	6.010s	297.580us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.960s	33.802us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	2.460s	130.024us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.010s	297.580us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	intr_test	keymgr_dpe_intr_test	2.160s	26.176us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	2.880s	26.411us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	4.400s	371.749us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	4.400s	371.749us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	2.420s	16.525us	5	5	100.00
		keymgr_dpe_csr_rw	2.460s	130.024us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.010s	297.580us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.720s	316.021us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	2.420s	16.525us	5	5	100.00
		keymgr_dpe_csr_rw	2.460s	130.024us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.010s	297.580us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.720s	316.021us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	10.520s	2.415ms	5	5	100.00
		keymgr_dpe_tl_intg_err	8.870s	482.753us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.750s	909.576us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.750s	909.576us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.750s	909.576us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.750s	909.576us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	7.740s	406.776us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	10.520s	2.415ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	10.520s	2.415ms	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			310	310	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.07	97.57	90.66	63.14	76.92	94.89	98.57	17.75