KMAC/MASKED Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.586m	4.620ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.340s	222.226us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.710s	17.984us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.560s	1.122ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.980s	886.665us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.980s	312.745us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.710s	17.984us	20	20	100.00
		kmac_csr_aliasing	9.980s	886.665us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.180s	12.625us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	3.020s	68.104us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	55.668m	137.672ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.228m	78.469ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.501m	257.954ms	5	5	100.00
		kmac_test_vectors_sha3_256	43.388m	345.997ms	5	5	100.00
		kmac_test_vectors_sha3_384	25.467m	66.664ms	5	5	100.00
		kmac_test_vectors_sha3_512	19.390m	178.814ms	5	5	100.00
		kmac_test_vectors_shake_128	41.351m	200.097ms	5	5	100.00
		kmac_test_vectors_shake_256	35.191m	62.324ms	5	5	100.00
		kmac_test_vectors_kmac	4.520s	335.121us	5	5	100.00
		kmac_test_vectors_kmac_xof	5.040s	431.828us	5	5	100.00
V2	sideload	kmac_sideload	8.258m	34.805ms	50	50	100.00
V2	app	kmac_app	6.977m	14.198ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.953m	82.793ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.901m	23.655ms	50	50	100.00
V2	error	kmac_error	8.750m	22.219ms	50	50	100.00
V2	key_error	kmac_key_error	19.470s	8.904ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.140s	385.648us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.630s	5.412ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	30.920s	7.575ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.365m	24.290ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	57.160s	2.986ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.676m	33.737ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.330s	37.628us	50	50	100.00
V2	alert_test	kmac_alert_test	2.370s	28.594us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.230s	677.501us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.230s	677.501us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.340s	222.226us	5	5	100.00
		kmac_csr_rw	2.710s	17.984us	20	20	100.00
		kmac_csr_aliasing	9.980s	886.665us	5	5	100.00
		kmac_same_csr_outstanding	4.170s	459.780us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.340s	222.226us	5	5	100.00
		kmac_csr_rw	2.710s	17.984us	20	20	100.00
		kmac_csr_aliasing	9.980s	886.665us	5	5	100.00
		kmac_same_csr_outstanding	4.170s	459.780us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.410s	104.720us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.410s	104.720us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.410s	104.720us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.410s	104.720us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.360s	317.232us	12	20	60.00
V2S	tl_intg_err	kmac_sec_cm	1.664m	7.711ms	5	5	100.00
		kmac_tl_intg_err	6.160s	596.435us	15	20	75.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.160s	596.435us	15	20	75.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	57.160s	2.986ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.586m	4.620ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.258m	34.805ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.410s	104.720us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.664m	7.711ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.664m	7.711ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.664m	7.711ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.586m	4.620ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	57.160s	2.986ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.664m	7.711ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.745m	171.082ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.586m	4.620ms	49	50	98.00
V2S		TOTAL			62	75	82.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.882m	3.175ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			922	940	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.24	99.09	94.47	99.89	78.87	97.09	99.37	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 12 failures:

Test kmac_tl_intg_err has 5 failures.

0.kmac_tl_intg_err.79635226738356253409103422160305018356393303875590250549801128826722336077207
Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
  UVM_ERROR @  17829044 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_10_rd_A
  UVM_INFO @  17829044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_tl_intg_err.25302563413790294191179126742947068328094880596205075361087510072941599671019
Line 83, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  26064560 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  26064560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

2.kmac_shadow_reg_errors_with_csr_rw.1891260187622585078554012300598578658582236519937292729007401479096303493912
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  22497685 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  22497685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_shadow_reg_errors_with_csr_rw.54137882576246248056490500726996840531856866333606875780162811562043137753965
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  21837700 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  21837700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 1.kmac_stress_all_with_rand_reset.103289573064792729581330804018678805168792525567220136878855726966822207334484
    Line 151, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4963944310 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 4963944310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.87025117430559532477746431317836671861937426875362887406848393466342337884362
    Line 216, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3174812839 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3174812839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 3.kmac_shadow_reg_errors_with_csr_rw.36986151933370734302980068350848864554306333882524442666500546926323936491380
    Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @   9066905 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (623709576 [0x252d0d88] vs 0 [0x0]) Regname: kmac_reg_block.prefix_3 reset value: 0x0
  UVM_INFO @   9066905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_smoke has 1 failures.
  - 49.kmac_smoke.68730408062505117916028954713837319719719335491396820769902954289148496413706
    Line 72, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/49.kmac_smoke/latest/run.log
```
  UVM_ERROR @  42798416 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  42798416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```