KMAC/UNMASKED Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.067m	6.345ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.490s	95.754us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.770s	51.897us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.850s	3.880ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.420s	388.164us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.270s	123.106us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.770s	51.897us	20	20	100.00
		kmac_csr_aliasing	8.420s	388.164us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.410s	29.132us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.660s	36.001us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.004m	363.775ms	50	50	100.00
V2	burst_write	kmac_burst_write	16.322m	61.938ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.952m	294.782ms	5	5	100.00
		kmac_test_vectors_sha3_256	31.832m	964.616ms	5	5	100.00
		kmac_test_vectors_sha3_384	21.019m	86.088ms	5	5	100.00
		kmac_test_vectors_sha3_512	11.491m	9.214ms	5	5	100.00
		kmac_test_vectors_shake_128	32.373m	437.724ms	5	5	100.00
		kmac_test_vectors_shake_256	21.395m	16.729ms	5	5	100.00
		kmac_test_vectors_kmac	4.400s	435.491us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.210s	102.809us	5	5	100.00
V2	sideload	kmac_sideload	8.222m	249.926ms	50	50	100.00
V2	app	kmac_app	5.177m	29.973ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.285m	14.994ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.826m	20.885ms	50	50	100.00
V2	error	kmac_error	7.818m	54.206ms	50	50	100.00
V2	key_error	kmac_key_error	19.300s	24.831ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.747m	10.052ms	37	50	74.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.430s	11.181ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	34.850s	1.786ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.283m	14.970ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	54.460s	2.904ms	50	50	100.00
V2	stress_all	kmac_stress_all	36.279m	322.381ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.410s	28.362us	50	50	100.00
V2	alert_test	kmac_alert_test	2.330s	258.002us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.650s	61.614us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.650s	61.614us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.490s	95.754us	5	5	100.00
		kmac_csr_rw	2.770s	51.897us	20	20	100.00
		kmac_csr_aliasing	8.420s	388.164us	5	5	100.00
		kmac_same_csr_outstanding	4.110s	222.803us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.490s	95.754us	5	5	100.00
		kmac_csr_rw	2.770s	51.897us	20	20	100.00
		kmac_csr_aliasing	8.420s	388.164us	5	5	100.00
		kmac_same_csr_outstanding	4.110s	222.803us	20	20	100.00
V2		TOTAL			727	740	98.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.340s	48.622us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.340s	48.622us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.340s	48.622us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.340s	48.622us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.230s	707.763us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.464m	11.551ms	5	5	100.00
		kmac_tl_intg_err	4.950s	224.326us	13	20	65.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.950s	224.326us	13	20	65.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.460s	2.904ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.067m	6.345ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.222m	249.926ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.340s	48.622us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.464m	11.551ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.464m	11.551ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.464m	11.551ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.067m	6.345ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.460s	2.904ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.464m	11.551ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.758m	14.538ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.067m	6.345ms	50	50	100.00
V2S		TOTAL			64	75	85.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.313m	6.651ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			910	940	96.81

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.98	97.17	94.42	100.00	74.38	95.98	99.35	96.56

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 11 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

0.kmac_shadow_reg_errors_with_csr_rw.45691272203017321527314940877072254575458993532628899713759411141725687813135
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  23106976 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  23106976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.kmac_shadow_reg_errors_with_csr_rw.108927900850829250820651991082233252131848660856327704893929730513239175081367
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  45768277 ps: (kmac_csr_assert_fpv.sv:517) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  45768277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_tl_intg_err has 7 failures.

4.kmac_tl_intg_err.24125501649351321687211402901046633498682354614361573969920995951089140601250
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  35836136 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  35836136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_tl_intg_err.105958372891527168868780684742375091953854870425289969786777034035550960247340
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  11464118 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  11464118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 0.kmac_stress_all_with_rand_reset.60379326295996555349846385311332698355932686638851872856703497233573574394064
    Line 289, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6650646529 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6650646529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.62646037440549548221857122094357537684780834824561562714474695664911954534333
    Line 201, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19464296518 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 19464296518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 4.kmac_stress_all_with_rand_reset.48989922188938295258302885500305214262460303428450984354988706459342274452359
    Line 107, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2659658085 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2659658085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.kmac_stress_all_with_rand_reset.46378653824620152144936267774183882798906766138482422276140838354450463926871
    Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7219746239 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7219746239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 18.kmac_sideload_invalid.19509299940542212941327055225055997432353682705516681391759072246051109188618
    Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10025138777 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5f55c000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10025138777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 42.kmac_sideload_invalid.40940316666634585972890113700570934012234089729261943508394468672128449586377
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10165110851 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaaab6000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10165110851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 27.kmac_sideload_invalid.84967736788159634848584033956874248057455157949192538449195797737620097806858
    Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10052244924 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe7065000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
  UVM_INFO @ 10052244924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 36.kmac_sideload_invalid.112247542209211754345678803230451225526135668065524182877254520542676768118741
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/36.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10344328639 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7655b000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
  UVM_INFO @ 10344328639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 0.kmac_sideload_invalid.26054850513125108789406943585600358811509702956765544819972066352137860823266
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10016943251 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa7467000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10016943251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 7.kmac_sideload_invalid.23833128110568690433885862107769314491383219451092268444110913451318776238237
    Line 97, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10626977490 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x65407000, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
  UVM_INFO @ 10626977490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 11.kmac_sideload_invalid.57235513736287251779865669659502297513328172370922758645691149238287578923242
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10033618002 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x63986000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10033618002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 19.kmac_sideload_invalid.35928473140769097754037438526104756626963726187203425944948129287772132207250
    Line 88, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10375408865 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2de88000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
  UVM_INFO @ 10375408865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 20.kmac_sideload_invalid.105993365810731881589934936847855324184439757692150524349891096296918241257325
    Line 94, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10156328293 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8a35a000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
  UVM_INFO @ 10156328293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 29.kmac_sideload_invalid.103357096870347709150578170399856243051471409419763489185881539685957765777672
    Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10049994399 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfad14000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
  UVM_INFO @ 10049994399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 34.kmac_sideload_invalid.98512488243168581253285248718362636878327013642728327725323636629695060297805
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/34.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10061662219 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x90ad6000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10061662219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 43.kmac_sideload_invalid.24332215186403057555263073443271514553949393972290907280877112640657259274531
    Line 100, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10186633376 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb3bf1000, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
  UVM_INFO @ 10186633376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 48.kmac_sideload_invalid.62561192909566594211462206374046079250798432359989510928474356990438717180888
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/48.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10017589374 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb1e44000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10017589374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```