OTBN Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	41.339us	1	1	100.00
V1	single_binary	otbn_single	42.000s	498.676us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	16.000s	42.359us	5	5	100.00
V1	csr_rw	otbn_csr_rw	9.000s	24.304us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	12.000s	349.861us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	24.665us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	21.000s	88.566us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	9.000s	24.304us	20	20	100.00
		otbn_csr_aliasing	8.000s	24.665us	5	5	100.00
V1	mem_walk	otbn_mem_walk	38.000s	1.248ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	21.000s	354.960us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.667m	443.615us	10	10	100.00
V2	multi_error	otbn_multi_err	56.000s	176.426us	1	1	100.00
V2	back_to_back	otbn_multi	1.550m	193.566us	10	10	100.00
V2	stress_all	otbn_stress_all	6.650m	2.445ms	10	10	100.00
V2	lc_escalation	otbn_escalate	22.000s	78.417us	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	41.504us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	59.000s	227.080us	10	10	100.00
V2	alert_test	otbn_alert_test	13.000s	39.462us	50	50	100.00
V2	intr_test	otbn_intr_test	12.000s	23.073us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	22.000s	534.528us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	22.000s	534.528us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	16.000s	42.359us	5	5	100.00
		otbn_csr_rw	9.000s	24.304us	20	20	100.00
		otbn_csr_aliasing	8.000s	24.665us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	23.446us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	16.000s	42.359us	5	5	100.00
		otbn_csr_rw	9.000s	24.304us	20	20	100.00
		otbn_csr_aliasing	8.000s	24.665us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	23.446us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	16.000s	41.817us	10	10	100.00
		otbn_dmem_err	22.000s	229.023us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	110.096us	5	5	100.00
		otbn_controller_ispr_rdata_err	14.000s	64.458us	5	5	100.00
		otbn_mac_bignum_acc_err	21.000s	54.060us	5	5	100.00
		otbn_urnd_err	10.000s	11.121us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	19.081us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	39.977us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	29.493us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	6.650m	2.321ms	3	5	60.00
		otbn_tl_intg_err	1.650m	492.646us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.350m	765.462us	16	20	80.00
V2S	prim_fsm_check	otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	41.339us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	22.000s	229.023us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	41.817us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.650m	492.646us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	22.000s	78.417us	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	41.817us	10	10	100.00
		otbn_dmem_err	22.000s	229.023us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	41.504us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	19.081us	5	5	100.00
		otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	42.000s	498.676us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	41.817us	10	10	100.00
		otbn_dmem_err	22.000s	229.023us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	41.504us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	19.081us	5	5	100.00
		otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	22.000s	78.417us	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	41.817us	10	10	100.00
		otbn_dmem_err	22.000s	229.023us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	41.504us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	19.081us	5	5	100.00
		otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	42.000s	498.676us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	13.000s	22.117us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	54.993us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	32.000s	599.095us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	32.000s	599.095us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	30.531us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	16.000s	156.275us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	36.419us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	36.419us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	22.406us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	42.000s	498.676us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	42.000s	498.676us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	42.000s	498.676us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.550m	193.566us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	42.000s	498.676us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	42.000s	498.676us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	20.000s	125.612us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	42.000s	498.676us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.650m	2.321ms	3	5	60.00
V2S		TOTAL			153	163	93.87
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.533m	4.751ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			566	585	96.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.11	99.64	96.04	99.73	93.02	93.62	100.00	97.95	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test otbn_stress_all_with_rand_reset has 5 failures.
  - 0.otbn_stress_all_with_rand_reset.59600678459556132068650312830054865567278110581856862217413854052573080830019
    Line 163, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 730002580 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 730002580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.otbn_stress_all_with_rand_reset.114498246103679037670795526421705926865159664155780675145548433409321048678682
    Line 152, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 131958556 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 131958556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 2 failures:

Test otbn_escalate has 2 failures.

0.otbn_escalate.1359069821928222941490312447964146065884742621151584598563752527500189044654
Line 151, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

  UVM_ERROR @   5285521 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   5285521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_escalate.12226081556869520734970101302159136713312275027672986308710831069698985300188
Line 103, in log /nightly/runs/scratch/master/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  UVM_ERROR @   5138728 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   5138728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:

Test otbn_passthru_mem_tl_intg_err has 2 failures.

2.otbn_passthru_mem_tl_intg_err.43366892714388592960561747636270753373171396814808038276659534329126087059673
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @   2864466 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @   2864466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.otbn_passthru_mem_tl_intg_err.93802349462237064174590397883138566793355326936446828293361250692463926222040
Line 97, in log /nightly/runs/scratch/master/otbn-sim-xcelium/9.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @  58431336 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  58431336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

2.otbn_sec_cm.110883354007203419451136362105576546306807542612282770019389575962232652752083
Line 104, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 113948274 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 113948274 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @ 113948274 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @ 113948274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_cm.108557111740264861273314682743261898321723966231592946652978394327290922438558
Line 118, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 165281567 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 165281567 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @ 165281567 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @ 165281567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_escalate has 1 failures.

3.otbn_escalate.76244709933973763438516703132246611762425978662210330920843944391871105872244
Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14805594 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  14805594 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  14805594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_sec_wipe_err has 1 failures.

6.otbn_sec_wipe_err.63594673494760247726498115462904078310614880948192535307722129668889977648111
Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22405851 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  22405851 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  22405851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
- Test otbn_passthru_mem_tl_intg_err has 2 failures.
  - 17.otbn_passthru_mem_tl_intg_err.58774773810734142572557963434864409355992476989396965805877948061415974346481
    Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/17.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   9803462 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   9803462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 19.otbn_passthru_mem_tl_intg_err.57633681063550464958906998200899143252375291178898223226457528106132245623741
    Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/19.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   4054674 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   4054674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed has 1 failures:

Test otbn_partial_wipe has 1 failures.

0.otbn_partial_wipe.7743635957903428687322927195095754324830625511701988502339384692086412151199
Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 6480714 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
  UVM_ERROR @   6480714 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
  UVM_INFO @   6480714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.102664523454445548794650525088183698381776891683390509984529666357915775188798
    Line 382, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1005986346 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1005986346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 4.otbn_partial_wipe.33986208192306673628497280432237349713769752767951091443575643215452898490941
    Line 104, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 3566936 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3566936 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3566936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 7.otbn_rf_base_intg_err.10661325273851993190025272276778629819604724406261160458024100569725365650595
    Line 108, in log /nightly/runs/scratch/master/otbn-sim-xcelium/7.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  25645282 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
  UVM_INFO @  25645282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```