ROM_CTRL/32KB Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.890s	236.105us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.630s	215.913us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	8.160s	554.772us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.000s	312.374us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.520s	2.103ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	9.330s	904.221us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	8.160s	554.772us	20	20	100.00
		rom_ctrl_csr_aliasing	8.520s	2.103ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.260s	2.089ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.330s	176.028us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.390s	182.713us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	28.760s	2.181ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	10.340s	3.153ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.440s	595.478us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.880s	127.241us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.880s	127.241us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.630s	215.913us	5	5	100.00
		rom_ctrl_csr_rw	8.160s	554.772us	20	20	100.00
		rom_ctrl_csr_aliasing	8.520s	2.103ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.830s	172.436us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.630s	215.913us	5	5	100.00
		rom_ctrl_csr_rw	8.160s	554.772us	20	20	100.00
		rom_ctrl_csr_aliasing	8.520s	2.103ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.830s	172.436us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.105m	21.800ms	19	20	95.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	31.370s	3.601ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.503m	934.215us	5	5	100.00
		rom_ctrl_tl_intg_err	1.013m	985.263us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.503m	934.215us	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.503m	934.215us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.105m	21.800ms	19	20	95.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.105m	21.800ms	19	20	95.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.105m	21.800ms	19	20	95.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.105m	21.800ms	19	20	95.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.105m	21.800ms	19	20	95.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.503m	934.215us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.503m	934.215us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.890s	236.105us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.890s	236.105us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.890s	236.105us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.013m	985.263us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.105m	21.800ms	19	20	95.00
		rom_ctrl_kmac_err_chk	10.340s	3.153ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.105m	21.800ms	19	20	95.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.105m	21.800ms	19	20	95.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.105m	21.800ms	19	20	95.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	31.370s	3.601ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.503m	934.215us	5	5	100.00
V2S		TOTAL			64	65	98.46
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	8.636m	5.456ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			265	266	99.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	100.00	99.41	100.00	100.00	100.00	98.97	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 3.rom_ctrl_corrupt_sig_fatal_chk.111793964400606365085354216600254578799981732645360763416495950384594606816334
      Line 81, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1459792930 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1459792930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---