RV_TIMER Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.100s	105.656us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.880s	54.977us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.240s	27.578us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.630s	1.545ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.230s	19.443us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.460s	29.771us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.240s	27.578us	20	20	100.00
		rv_timer_csr_aliasing	2.230s	19.443us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	10.610s	7.041ms	20	20	100.00
V2	disabled	rv_timer_disabled	5.130s	1.886ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.910m	346.900ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.910m	346.900ms	10	10	100.00
V2	stress	rv_timer_stress_all	7.920s	3.951ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.050s	30.376us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.050s	15.578us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.830s	216.464us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.830s	216.464us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.880s	54.977us	5	5	100.00
		rv_timer_csr_rw	2.240s	27.578us	20	20	100.00
		rv_timer_csr_aliasing	2.230s	19.443us	5	5	100.00
		rv_timer_same_csr_outstanding	2.070s	66.673us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.880s	54.977us	5	5	100.00
		rv_timer_csr_rw	2.240s	27.578us	20	20	100.00
		rv_timer_csr_aliasing	2.230s	19.443us	5	5	100.00
		rv_timer_same_csr_outstanding	2.070s	66.673us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.500s	100.897us	5	5	100.00
		rv_timer_tl_intg_err	2.680s	168.777us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.680s	168.777us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	47.520s	22.303ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	2.100s	120.127us	10	10	100.00
		rv_timer_max	2.120s	14.184us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.95	100.00	100.00	100.00	--	100.00	100.00	99.71