SPI_DEVICE/1R1W Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.985m	158.748ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.950s	165.467us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.120s	220.891us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.870s	18.044ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.060s	319.250us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.260s	506.567us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.120s	220.891us	20	20	100.00
		spi_device_csr_aliasing	20.060s	319.250us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.140s	10.313us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.540s	119.203us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.360s	49.828us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.260s	4.159us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.800s	3.525us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	4.690s	650.521us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	4.690s	650.521us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.720s	9.493ms	50	50	100.00
		spi_device_tpm_sts_read	2.520s	106.754us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.103m	41.049ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	55.880s	14.794ms	50	50	100.00
		spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.930s	37.405ms	50	50	100.00
		spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.930s	37.405ms	50	50	100.00
		spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	46.320s	21.819ms	50	50	100.00
		spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	46.320s	21.819ms	50	50	100.00
		spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	46.320s	21.819ms	50	50	100.00
		spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	46.320s	21.819ms	50	50	100.00
		spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	46.320s	21.819ms	50	50	100.00
		spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	35.900s	6.464ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.837m	16.196ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.837m	16.196ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.837m	16.196ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.435m	59.507ms	50	50	100.00
		spi_device_read_buffer_direct	20.630s	7.114ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.837m	16.196ms	50	50	100.00
		spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.100m	73.422ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	42.350s	22.479ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	42.350s	22.479ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.985m	158.748ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.263m	38.397ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.499m	95.579ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.320s	53.173us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.330s	22.442us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.000s	1.084ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.000s	1.084ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.950s	165.467us	5	5	100.00
		spi_device_csr_rw	4.120s	220.891us	20	20	100.00
		spi_device_csr_aliasing	20.060s	319.250us	5	5	100.00
		spi_device_same_csr_outstanding	5.820s	439.444us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.950s	165.467us	5	5	100.00
		spi_device_csr_rw	4.120s	220.891us	20	20	100.00
		spi_device_csr_aliasing	20.060s	319.250us	5	5	100.00
		spi_device_same_csr_outstanding	5.820s	439.444us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.870s	361.066us	5	5	100.00
		spi_device_tl_intg_err	23.770s	815.844us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.770s	815.844us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.761m	712.833ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.54	98.98	96.55	83.54	89.36	98.39	95.66	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.53382856899491971280522123867631391648260054507327344308428005769100832164830
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1516704 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[81])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1516704 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1516704 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[977])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.77457044485240042833907152301291316787058453644965920309321805730997999029274
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4567589 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[18])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4567589 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4567589 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[914])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.17935887392395512448252908215733673158980773291385314719988853981021991217169
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    847057 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe27bb9 [111000100111101110111001] vs 0x0 [0])
        UVM_ERROR @    882057 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc28409 [110000101000010000001001] vs 0x0 [0])
        UVM_ERROR @    954057 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2d98da [1011011001100011011010] vs 0x0 [0])
        UVM_ERROR @    998057 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5815a3 [10110000001010110100011] vs 0x0 [0])
        UVM_ERROR @   1040057 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x685b51 [11010000101101101010001] vs 0x0 [0])