SPI_HOST Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.233m	3.932ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	47.980us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	41.313us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	618.987us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	36.916us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	46.614us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	41.313us	20	20	100.00
		spi_host_csr_aliasing	4.000s	36.916us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	21.735us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	19.775us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	5.000s	36.297us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	32.000s	4.674ms	50	50	100.00
		spi_host_error_cmd	5.000s	21.227us	50	50	100.00
		spi_host_event	11.550m	44.087ms	50	50	100.00
V2	clock_rate	spi_host_speed	10.000s	242.879us	50	50	100.00
V2	speed	spi_host_speed	10.000s	242.879us	50	50	100.00
V2	chip_select_timing	spi_host_speed	10.000s	242.879us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	46.000s	1.416ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	58.012us	50	50	100.00
V2	cpol_cpha	spi_host_speed	10.000s	242.879us	50	50	100.00
V2	full_cycle	spi_host_speed	10.000s	242.879us	50	50	100.00
V2	duplex	spi_host_smoke	1.233m	3.932ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.233m	3.932ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.250m	2.601ms	50	50	100.00
V2	spien	spi_host_spien	1.350m	13.817ms	49	50	98.00
V2	stall	spi_host_status_stall	25.433m	172.047ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	30.000s	5.683ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	32.000s	4.674ms	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	37.192us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	30.274us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	392.115us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	392.115us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	47.980us	5	5	100.00
		spi_host_csr_rw	5.000s	41.313us	20	20	100.00
		spi_host_csr_aliasing	4.000s	36.916us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	81.791us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	47.980us	5	5	100.00
		spi_host_csr_rw	5.000s	41.313us	20	20	100.00
		spi_host_csr_aliasing	4.000s	36.916us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	81.791us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	850.182us	20	20	100.00
		spi_host_sec_cm	5.000s	248.520us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	850.182us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	8.450m	36.219ms	10	10	100.00
		TOTAL			836	840	99.52

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.25	96.78	93.27	98.69	94.26	88.02	100.00	97.27	90.42

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 2 failures:

Test spi_host_status_stall has 2 failures.

32.spi_host_status_stall.24711592787897986145454219108309065169051756748803702901365060812249878604902
Line 8048, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/32.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 4672609711 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 4672609711 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=4672610000 ps
  UVM_INFO @ 4672609711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.spi_host_status_stall.73668848135238147249514892978826749588053374717151646522058054667641782171285
Line 771, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/40.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 301161942 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 301161942 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=301162000 ps
  UVM_INFO @ 301161942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_host_base_vseq.sv:234) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
- Test spi_host_spien has 1 failures.
  - 16.spi_host_spien.8660974643035467030275917521721769842372397261525741204407261177418570501178
    Line 377, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/16.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 10467052035 ps: (spi_host_base_vseq.sv:234) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x4c453f54, Comparison=CompareOpEq, exp_data=0x0, call_count=80
  UVM_INFO @ 10467052035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 23.spi_host_status_stall.99293238461438088740478870380115571550872526891557915213573522040430697381609
    Line 872, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```