SRAM_CTRL/MAIN Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.635m	469.834us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.110s	25.506us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.200s	32.179us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.520s	121.617us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.120s	119.193us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.180s	393.357us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.200s	32.179us	20	20	100.00
		sram_ctrl_csr_aliasing	2.120s	119.193us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.391m	43.172ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.906m	72.902ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	20.497m	18.518ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.923m	7.550ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	37.869m	119.840ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	18.960m	16.388ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.357m	244.541ms	50	50	100.00
V2	executable	sram_ctrl_executable	20.701m	41.298ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.549m	2.531ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.239m	111.068ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.605m	768.827us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.657m	3.312ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.759m	3.382ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	24.149m	73.088ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.840s	1.403ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.306h	1.853s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.200s	27.142us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.740s	2.031ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.740s	2.031ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.110s	25.506us	5	5	100.00
		sram_ctrl_csr_rw	2.200s	32.179us	20	20	100.00
		sram_ctrl_csr_aliasing	2.120s	119.193us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.290s	68.631us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.110s	25.506us	5	5	100.00
		sram_ctrl_csr_rw	2.200s	32.179us	20	20	100.00
		sram_ctrl_csr_aliasing	2.120s	119.193us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.290s	68.631us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	57.030s	7.363ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.040s	7.323us	0	5	0.00
		sram_ctrl_tl_intg_err	4.880s	2.906ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.040s	7.323us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.880s	2.906ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.149m	73.088ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	24.149m	73.088ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.200s	32.179us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	20.701m	41.298ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	20.701m	41.298ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	20.701m	41.298ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.357m	244.541ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	10.990s	2.802ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	57.030s	7.363ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.220s	10.970ms	37	50	74.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.635m	469.834us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.635m	469.834us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	20.701m	41.298ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.040s	7.323us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.357m	244.541ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.040s	7.323us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.040s	7.323us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.635m	469.834us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.040s	7.323us	0	5	0.00
V2S		TOTAL			121	145	83.45
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.526m	7.964ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1166	1190	97.98

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	99.29	93.01	85.18	100.00	98.03	98.59	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 13 failures:
  • Test sram_ctrl_readback_err has 13 failures.

    • 5.sram_ctrl_readback_err.70390459846385475840101345264261784512344615378071044178479306706574952771321
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 3865047008 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x67) != exp (0x5d)
        UVM_INFO @ 3865047008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.sram_ctrl_readback_err.9628052960897901003335314435684541817064727827036156730204401702322868920797
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/11.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 4697234035 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x24) != exp (0x70)
        UVM_INFO @ 4697234035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 11 more failures.

• Offending 'reqfifo_rvalid' has 6 failures:
  • Test sram_ctrl_mubi_enc_err has 6 failures.

    • 12.sram_ctrl_mubi_enc_err.14746050424572257214777554685437757608988420972159868118373184721023488623682
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 5982207020 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 5982207020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 23.sram_ctrl_mubi_enc_err.79500626037011007891301402617451619134033256974090759422826416050408779498666
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/23.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 814261722 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 814261722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.27610049708405982862641560587304268620673102180227948852479812036268717889064
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1854832 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1854832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.41954489772255292118428005029976480291165097260958852147306103605895660447758
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4208888 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4208888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.30901910735985129255938946252543988121978077838183569664095966349839893136913
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   3988217 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   3988217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---