SRAM_CTRL/RET Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.631m	704.060us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.940s	37.953us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.090s	44.492us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.680s	1.429ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.950s	55.225us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.660s	106.719us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.090s	44.492us	20	20	100.00
		sram_ctrl_csr_aliasing	1.950s	55.225us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	14.850s	2.042ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.930s	2.049ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	22.179m	21.829ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.921m	10.586ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.917m	21.626ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.807m	14.224ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.550s	960.086us	50	50	100.00
V2	executable	sram_ctrl_executable	23.103m	20.049ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.657m	1.746ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.191m	79.059ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.598m	135.337us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.593m	2.938ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.699m	287.020us	50	50	100.00
V2	regwen	sram_ctrl_regwen	20.631m	63.841ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.440s	30.417us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.119h	328.009ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.220s	12.965us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.400s	230.903us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.400s	230.903us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.940s	37.953us	5	5	100.00
		sram_ctrl_csr_rw	2.090s	44.492us	20	20	100.00
		sram_ctrl_csr_aliasing	1.950s	55.225us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.110s	23.168us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.940s	37.953us	5	5	100.00
		sram_ctrl_csr_rw	2.090s	44.492us	20	20	100.00
		sram_ctrl_csr_aliasing	1.950s	55.225us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.110s	23.168us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.420s	1.363ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.330s	33.333us	0	5	0.00
		sram_ctrl_tl_intg_err	4.910s	2.978ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.330s	33.333us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.910s	2.978ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.631m	63.841ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	20.631m	63.841ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.090s	44.492us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.103m	20.049ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.103m	20.049ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.103m	20.049ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.550s	960.086us	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.820s	384.777us	41	50	82.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.420s	1.363ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.690s	141.288us	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.631m	704.060us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.631m	704.060us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.103m	20.049ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.330s	33.333us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.550s	960.086us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.330s	33.333us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.330s	33.333us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.631m	704.060us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.330s	33.333us	0	5	0.00
V2S		TOTAL			120	145	82.76
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.604m	1.859ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1165	1190	97.90

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.26	93.01	85.10	100.00	97.99	98.58	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 11 failures:
  • Test sram_ctrl_readback_err has 11 failures.

    • 1.sram_ctrl_readback_err.106151661884719187772395387070094117148475583121021145986532548245125644663425
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  87768423 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x4e) != exp (0x66)
        UVM_INFO @  87768423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_readback_err.11973753754605075208708473553734315765253230926711855115487893214218989212176
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  34536560 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x1d) != exp (0xa)
        UVM_INFO @  34536560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• Offending 'reqfifo_rvalid' has 9 failures:
  • Test sram_ctrl_mubi_enc_err has 9 failures.

    • 0.sram_ctrl_mubi_enc_err.35145530575133687712958806502680176003659816911443786316660396578568563952666
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 108633922 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 108633922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_mubi_enc_err.107140149974298189411112124388842584773864552548434463887053720443947728242631
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 134908436 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 134908436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.99822786604840484040408552813552510140586471083276845071255561990595205874109
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1720503 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1720503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.27514534305990246434356766762449297126693780349901389656471211517450301134693
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6248116 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6248116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.78990976586364189669164345941762771058929379804223173966248364940112564028210
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @  33332582 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @  33332582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---