UART Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	42.140s	11.051ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.270s	14.676us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.340s	14.698us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.590s	75.603us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.160s	18.837us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.620s	20.650us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.340s	14.698us	20	20	100.00
		uart_csr_aliasing	2.160s	18.837us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.990m	147.893ms	50	50	100.00
V2	parity	uart_smoke	42.140s	11.051ms	50	50	100.00
		uart_tx_rx	2.990m	147.893ms	50	50	100.00
V2	parity_error	uart_intr	9.896m	394.121ms	50	50	100.00
		uart_rx_parity_err	5.911m	226.173ms	50	50	100.00
V2	watermark	uart_tx_rx	2.990m	147.893ms	50	50	100.00
		uart_intr	9.896m	394.121ms	50	50	100.00
V2	fifo_full	uart_fifo_full	8.027m	227.880ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.954m	152.735ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.675m	180.482ms	299	300	99.67
V2	rx_frame_err	uart_intr	9.896m	394.121ms	50	50	100.00
V2	rx_break_err	uart_intr	9.896m	394.121ms	50	50	100.00
V2	rx_timeout	uart_intr	9.896m	394.121ms	50	50	100.00
V2	perf	uart_perf	20.412m	35.981ms	49	50	98.00
V2	sys_loopback	uart_loopback	26.840s	8.857ms	50	50	100.00
V2	line_loopback	uart_loopback	26.840s	8.857ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.095m	119.052ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.322m	33.834ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	25.700s	14.187ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.076m	6.835ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	13.500m	89.126ms	50	50	100.00
V2	stress_all	uart_stress_all	16.490m	360.542ms	50	50	100.00
V2	alert_test	uart_alert_test	2.150s	110.743us	50	50	100.00
V2	intr_test	uart_intr_test	2.310s	15.192us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.340s	149.571us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.340s	149.571us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.270s	14.676us	5	5	100.00
		uart_csr_rw	2.340s	14.698us	20	20	100.00
		uart_csr_aliasing	2.160s	18.837us	5	5	100.00
		uart_same_csr_outstanding	2.410s	32.079us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.270s	14.676us	5	5	100.00
		uart_csr_rw	2.340s	14.698us	20	20	100.00
		uart_csr_aliasing	2.160s	18.837us	5	5	100.00
		uart_same_csr_outstanding	2.410s	32.079us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	2.420s	77.028us	5	5	100.00
		uart_tl_intg_err	2.740s	99.625us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.740s	99.625us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.966m	20.428ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1316	1320	99.70

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.17	98.25	91.55	--	98.14	100.00	99.53

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 28.uart_stress_all_with_rand_reset.72979998167589157745657379168068008809140942476476772432345553801181877026722
      Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @   1901606 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
        UVM_INFO @   7343679 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @   7384915 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 1/5
      

• UVM_ERROR (cip_base_vseq.sv:832) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 31.uart_stress_all_with_rand_reset.9450347945039520965384566248532669711271896208596523820672389277373370536791
      Line 131, in log /nightly/runs/scratch/master/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2146877787 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2146877787 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 6/10
        UVM_INFO @ 2146982262 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 6/10
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_perf has 1 failures.

    • 47.uart_perf.43105050480406007881831905289125353348692810408619901715122539773783808949221
      Line 76, in log /nightly/runs/scratch/master/uart-sim-vcs/47.uart_perf/latest/run.log

        UVM_ERROR @ 10290364202 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
        UVM_INFO @ 10566072290 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 8/8
        UVM_INFO @ 10788368146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 1 failures:

  • Test uart_fifo_reset has 1 failures.

    • 110.uart_fifo_reset.78411202113300435012310794632717643999201870439862614636084949045087313913760
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/110.uart_fifo_reset/latest/run.log

        UVM_ERROR @   4678840 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 1193159133 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/6
        UVM_INFO @ 1593232807 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/6
        UVM_INFO @ 2951194412 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/6
        UVM_INFO @ 37176567594 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/6