CHIP Simulation Results

Friday May 09 2025 17:39:49 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.481m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.481m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.832m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	2.028m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.813m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.644m	5.332ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.644m	5.332ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.644m	5.332ms	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	47.520s	10.220us	0	3	0.00
		chip_sw_example_manufacturer	3.132m		0	3	0.00
		chip_sw_example_concurrency	5.830m	5.642ms	3	3	100.00
		chip_sw_uart_smoketest_signed	21.486s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	17.660s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	17.500s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	17.500s		0	3	0.00
V1	xbar_smoke	xbar_smoke	36.200s	67.781us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.710m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.767m	8.182ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	6.292m	5.438ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.435m		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	58.545s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.838m		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.777m		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.990s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.990s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.854m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.075m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	3.768m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	3.768m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.296m	3.407ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	4.553m	3.463ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.763m	13.539ms	0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	18.793s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	18.466s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	29.401m	33.758ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	7.467m	5.527ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	33.654m	18.018ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	33.654m	18.018ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	22.158s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.797m	5.432ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.797m	5.432ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.405m	18.015ms	0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.654m	3.812ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.299m	4.890ms	3	3	100.00
		chip_sw_aes_idle	5.683m	5.195ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.675m	5.450ms	3	3	100.00
		chip_sw_kmac_idle	4.280m	3.846ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	19.028m	12.018ms	0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	17.283m	12.015ms	0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	19.405m	12.022ms	0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	21.728m	12.016ms	0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	18.530s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	19.658s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	19.179s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	17.682s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.355s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.720s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.128s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.530s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	19.658s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	19.179s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	17.682s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.355s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.720s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.128s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	34.066s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.574m	10.300us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.438m	10.140us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.334m	10.180us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.303m	10.100us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	21.013s		0	3	0.00
		chip_sw_clkmgr_jitter	4.614m	4.670ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.753m	4.974ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	19.919s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.278m	10.200us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.346m	10.340us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1.476m	10.240us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.155m	10.140us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.260m	10.100us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	18.951s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	18.781s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	19.022s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	18.817s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	34.973m	12.357ms	92	100	92.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	14.090m	15.165ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	6.797m	5.432ms	0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	22.782s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	14.090m	15.165ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	46.598s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	52.124s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	26.831s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	17.131s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	31.296s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	34.973m	12.357ms	92	100	92.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.763m	13.539ms	0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	41.143m	20.019ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.981m	8.948ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.578m	11.212ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.568m	5.429ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	34.973m	12.357ms	92	100	92.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	18.764s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	18.459s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	34.973m	12.357ms	92	100	92.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	29.741s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.578m	11.212ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	20.842s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	26.097s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	24.098s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	18.623s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	19.979s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	34.014s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	18.459s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	40.707s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.845m		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	40.707s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	40.707s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	40.707s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.752m	7.251ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	31.365s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	45.575s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	39.052s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.301s		0	3	0.00
		chip_sw_lc_ctrl_transition	40.707s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	8.337m	7.810ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	15.216m	11.463ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	17.522s		0	3	0.00
		chip_prim_tl_access	19.545m	22.787ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.530s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	19.658s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	19.179s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	17.682s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.355s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.720s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.128s		0	3	0.00
		chip_rv_dm_lc_disabled	29.401m	33.758ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.986m	5.198ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	1.574m	10.300us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.958m	4.615ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.683m	5.195ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.095m	4.539ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	1.438m	10.140us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.675m	5.450ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.440m	3.750ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.115m	5.797ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.303m	10.100us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.337m	7.810ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	40.707s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.198m	10.320us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	8.569m	6.158ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.280m	3.846ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	26.566s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	26.566s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	15.567s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	6.944m	5.101ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	19.243s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.337m	7.810ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.334m	10.180us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.087s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	34.066s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.299m	4.890ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.299m	4.890ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.299m	4.890ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	10.789m	5.786ms	3	3	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	15.216m	11.463ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	15.216m	11.463ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	13.088m	10.585ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	21.013s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	17.522s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	34.973m	12.357ms	92	100	92.00
		chip_sw_data_integrity_escalation	3.768m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	40.707s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	10.789m	5.786ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	8.337m	7.810ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	13.088m	10.585ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.526m	3.691ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	10.789m	5.786ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	8.337m	7.810ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	13.088m	10.585ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.526m	3.691ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	40.707s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	18.601s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.845m		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	31.365s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	45.575s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	39.052s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.301s		0	3	0.00
		chip_sw_lc_ctrl_transition	40.707s		0	15	0.00
		chip_prim_tl_access	19.545m	22.787ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	19.545m	22.787ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	18.301s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	13.275s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	18.781s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	34.066s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.574m	10.300us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.438m	10.140us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.334m	10.180us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.303m	10.100us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	21.013s		0	3	0.00
		chip_sw_clkmgr_jitter	4.614m	4.670ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	10.134m	5.655ms	3	3	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	10.134m	5.655ms	3	3	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	6.871m	3.769ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	5.414m	5.396ms	0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.883m	5.487ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	9.587m	5.028ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.386m	5.186ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	6.329m	5.172ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.526m	3.691ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	41.143m	20.019ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	41.143m	20.019ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	5.897m	4.248ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.314m	5.776ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.600m	4.451ms	3	3	100.00
		chip_sw_csrng_smoketest	5.654m	5.231ms	3	3	100.00
		chip_sw_gpio_smoketest	6.298m	5.665ms	3	3	100.00
		chip_sw_hmac_smoketest	6.820m	5.268ms	3	3	100.00
		chip_sw_kmac_smoketest	6.818m	5.712ms	3	3	100.00
		chip_sw_otbn_smoketest	7.905m	5.325ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.936m	4.753ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.425m	4.944ms	3	3	100.00
		chip_sw_rv_timer_smoketest	7.372m	4.895ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.566m	5.597ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.926m	5.350ms	3	3	100.00
		chip_sw_uart_smoketest	5.639m	4.452ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	20.662s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	21.486s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.710m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	17.038s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.651m	6.168ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.415m	3.676ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	5.851m	6.724ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.354m	4.838ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	39.429s		0	3	0.00
		chip_rv_dm_lc_disabled	29.401m	33.758ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	22.677s		0	3	0.00
		chip_sw_lc_walkthrough_prod	24.584s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	36.054s		0	3	0.00
		chip_sw_lc_walkthrough_rma	38.767s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	39.429s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	16.399s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	17.400s		0	3	0.00
		rom_volatile_raw_unlock	15.812s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	43.431s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.488m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.973m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	5.289m	5.233ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	5.289m	5.233ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	17.500s		0	3	0.00
		chip_same_csr_outstanding	18.970s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	17.500s		0	3	0.00
		chip_same_csr_outstanding	18.970s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	4.348m	520.710us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	15.740s	13.496us	100	100	100.00
		xbar_smoke_large_delays	8.805m	2.387ms	100	100	100.00
		xbar_smoke_slow_rsp	10.369m	2.229ms	100	100	100.00
		xbar_random_zero_delays	2.151m	83.000us	100	100	100.00
		xbar_random_large_delays	36.214m	12.425ms	100	100	100.00
		xbar_random_slow_rsp	54.635m	14.904ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	3.027m	244.370us	100	100	100.00
		xbar_error_and_unmapped_addr	2.520m	245.201us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	5.061m	522.785us	100	100	100.00
		xbar_error_and_unmapped_addr	2.520m	245.201us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	8.734m	830.374us	100	100	100.00
		xbar_access_same_device_slow_rsp	58.534m	19.021ms	72	100	72.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	3.994m	448.366us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	26.527m	3.038ms	100	100	100.00
		xbar_stress_all_with_error	28.834m	3.871ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	57.124m	6.785ms	99	100	99.00
		xbar_stress_all_with_reset_error	52.960m	6.584ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	17.990s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	18.553s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	18.383s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	17.945s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	18.863s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	18.783s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	18.898s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	18.155s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.742s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	18.242s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	15.760s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	18.316s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.861s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	19.094s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	19.586s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.896s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	19.509s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	19.081s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	19.348s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	15.474s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	18.446s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.798s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.027s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.162s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.905s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	17.296s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	14.927s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	14.999s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.959s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.001s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.567s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.159s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	15.153s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	17.514s		0	3	0.00
		rom_e2e_asm_init_dev	18.314s		0	3	0.00
		rom_e2e_asm_init_prod	17.823s		0	3	0.00
		rom_e2e_asm_init_prod_end	17.987s		0	3	0.00
		rom_e2e_asm_init_rma	17.709s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	18.778s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	16.104s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	18.548s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	18.297s		0	3	0.00
V2		TOTAL			1898	2429	78.14
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.826m	5.490ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	5.174m	5.341ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.256s		0	1	0.00
		rom_e2e_jtag_debug_dev	14.520s		0	1	0.00
		rom_e2e_jtag_debug_rma	13.886s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	18.484s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	34.973m	12.357ms	92	100	92.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	18.766s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.807m	13.041ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	16.872s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	18.260s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.256s		0	1	0.00
		rom_e2e_jtag_debug_dev	14.520s		0	1	0.00
		rom_e2e_jtag_debug_rma	13.886s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	15.822s		0	1	0.00
		rom_e2e_jtag_inject_dev	19.164s		0	1	0.00
		rom_e2e_jtag_inject_rma	14.681s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.449m		0	3	0.00
V3		TOTAL			1	20	5.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	27.682m	13.752ms	3	3	100.00
		chip_plic_all_irqs_0	12.208m	7.375ms	3	3	100.00
		chip_plic_all_irqs_10	12.746m	7.130ms	3	3	100.00
		chip_sw_dma_inline_hashing	6.650m	6.266ms	3	3	100.00
		chip_sw_dma_abort	5.128m	5.472ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	16.394s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	18.292s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	18.825s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	17.702s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	18.203s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	15.838s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	18.243s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	17.222s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	18.139s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	21.474s		0	3	0.00
		chip_sw_mbx_smoketest	7.295m	5.930ms	3	3	100.00
		TOTAL			2026	2659	76.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
75.62	74.55	78.13	66.13	--	80.91	66.93	87.06

Failure Buckets

Job returned non-zero exit code has 455 failures:

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.7998610754832084012906520349823667773407794475230673651654253392545388844329
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (72bc75)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 158.842s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_manufacturer.37718403365546418111329293039146283246259481620969665628827617678434159405979
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (84e835)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 5.377s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_data_integrity_escalation has 6 failures.

0.chip_sw_data_integrity_escalation.87516181285022931712048199225643957462803030494508949203760146162051189059273
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (dbdea2)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 210.828s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_data_integrity_escalation.3056965893232488792955341374231802377928634980084420823921360254720937747954
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f9a4d8)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 5.276s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 4 more failures.

Test chip_sw_sleep_pin_wake has 3 failures.

0.chip_sw_sleep_pin_wake.67992085940434054940167490107076146244707637526613183004226939240631946651345
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (50f808)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 154.285s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_wake.19555225831805194567452360342302930311395374213492445620124221445533701281271
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (fa1508)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 0.426s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_sleep_pin_retention has 3 failures.

0.chip_sw_sleep_pin_retention.17690173224798404111889144716530535158713855961709773466932313560531066500794
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (1f8c86)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 172.331s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_retention.77018169691663820092009598789499165312075160313688909223996462286182845725258
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (21ea40)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 0.273s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_uart_tx_rx has 5 failures.

0.chip_sw_uart_tx_rx.109032496910035914133545341442472382574099706262376690761851847614740970718757
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (fc3e93)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 134.564s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_uart_tx_rx.20532830332128614020542644410184748906753161127727896754122190775163317658048
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (433931)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 0.269s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 3 more failures.

... and 131 more tests.

Job timed out after * minutes has 29 failures:
- Test xbar_access_same_device_slow_rsp has 28 failures.
  - 2.xbar_access_same_device_slow_rsp.21353517476006657185568353226979326137615258342943975326013857792793750086617
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - 3.xbar_access_same_device_slow_rsp.22067797824737965813726748598060157941255335536134060650454580130793053348144
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 26 more failures.
- Test xbar_stress_all_with_rand_reset has 1 failures.
  - 56.xbar_stress_all_with_rand_reset.5650113887112483603307345911011474981372880862918950670841115109786296901546
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/56.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 27 failures:
- Test chip_sw_aes_enc_jitter_en has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en.108989776141103273966778775371931479713918057832797823457324824737082681959390
    Line 453, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en.115623573421027258796260340565794774490889811177343494332278750462810192195441
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_hmac_enc_jitter_en has 3 failures.
  - 0.chip_sw_hmac_enc_jitter_en.71413480209639086662469669861565926134931397989317796004615668287310114004584
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_enc_jitter_en.5111953141468014084386262325551733412783876040740579382513032262155861842262
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.43610837809010109501242700181091967456073008176579190795245689981078060925753
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.45418735663066334047342058800906959846721537838559257743315889664904427590696
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.25935285409467860190911260012971236847092023234036069000320604012981897003439
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_mode_kmac_jitter_en.73378365504438633906028476958014386513180472394461119451547287690292043274875
    Line 413, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.61477866257508898451995620253975008616527105750588819301843196535735300066630
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en_reduced_freq.13259396477618772116533722538504655599617241812339512870454299606205077399096
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 12 failures:

Test chip_sw_rstmgr_cpu_info has 3 failures.

0.chip_sw_rstmgr_cpu_info.6231326384703496110144713166094683062874869801880999411670231491325704442179
Line 551, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20017.404640 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20017.404640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_cpu_info.65758061533127011264216869800713145649638916125331510155525864719272459867289
Line 448, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20024.023376 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20024.023376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_irq has 3 failures.

0.chip_sw_aon_timer_irq.86610513668646994174720032427543283206036621380206389806058784078499064651168
Line 515, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.009238 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.009238 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_irq.92885201313342380352771823093079331434200644492647590893870058616680179556717
Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18019.020120 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18019.020120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 5 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.104530044460186567486130416386659230406573875461251655944034436595444318105139
Line 495, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18015.367658 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.367658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_sleep_wdog_sleep_pause.72937615453620484608132966779092563324884540386336359331282116874137762039978
Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.013807 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.013807 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

1.chip_sw_clkmgr_off_hmac_trans.35948179747937722814501921628324072707695745201320912140788105276511559805360
Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12015.144690 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.144690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 12 failures:
- Test chip_tl_errors has 12 failures.
  - 1.chip_tl_errors.48473892317273024657778037134508082487096915697843474059656813412948485158554
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3981.141604 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3981.141604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_tl_errors.100475299417573679960562377022493102385568432749422126031362610502884604669561
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4256.747500 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4256.747500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 11 failures:

Test chip_sw_clkmgr_off_aes_trans has 3 failures.

0.chip_sw_clkmgr_off_aes_trans.74540209831372211211275966116032119010628435974995270585632198308927661153160
Line 444, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12021.827581 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12021.827581 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_aes_trans.59549339346056294427356802237117524842674677892812314697394270650329810573160
Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12015.825077 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.825077 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_clkmgr_off_hmac_trans has 2 failures.

0.chip_sw_clkmgr_off_hmac_trans.1965446926014333637199839440497474483148119300006416855718588336558457133987
Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12016.161091 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.161091 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_clkmgr_off_hmac_trans.78887249633528020549382369942377341738065057643212349911924377844437045943985
Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12020.469734 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12020.469734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 3 failures.

0.chip_sw_clkmgr_off_kmac_trans.81992210571042838322715381221165033168695101385086186889284379590558330088561
Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12016.780204 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.780204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_kmac_trans.27804502956383490788840261725087782014713521074001988313399737771046233797052
Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12017.884442 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.884442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_clkmgr_off_otbn_trans has 3 failures.

0.chip_sw_clkmgr_off_otbn_trans.35364770692254104461330852116377673280454697130245824827160153881840480869867
Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12025.278749 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12025.278749 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_otbn_trans.97103742293547025619659411589081945156425335032397420136230447432212878364067
Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12017.541972 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.541972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
- Test chip_padctrl_attributes has 10 failures.
  - 0.chip_padctrl_attributes.1508902373249274489401682467314066454319171616733073015287065324251623908813
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.chip_padctrl_attributes.106947526885921994009900940024087826702332011453446187435965047444596863849192
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.89690490621846280013615225506696466385651484772783202060601210964802487533213
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_bit_bash.41750800703112842066513503197564029518566465142447625585095520565347081539242
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.101109741620161399878937913712944031953330901538678483555496932712796712670774
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_aliasing.86803965537264930770631303946660109855479176555822526711568697048387261895774
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.109146335814757518785647798383919928290102111942288759463530722260165779560971
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_same_csr_outstanding.108141859877567869506459805663388082463797207733724504050767606722827954497146
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 6 failures:

Test chip_sw_keymgr_dpe_key_derivation has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation.32906753844358981778651435663342895277325635536990942223080647662789909461266
Line 466, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 5486.292040 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (22944846787868704317159719435653787784412105633823116928158428749682795248202 [0x32ba52b4524950fa15c21967dd366124d72d9eec4564ac877d2b9a45fc4a7a4a] vs 102534059777888024575774976611731224500487852793000219443008928608612905885109 [0xe2b038a3d4b87be69a7167daae3ee6a13b0bf4b2200c552b2efbb043809f9db5])
  UVM_INFO @ 5486.292040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation.54976556463166138003694933952972960552291934065037149486379889064671946837704
Line 475, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 7809.679680 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (112400244913243090414434535938991322527264601845534591629113628079960310957850 [0xf88048bdb5b1670152f2d0440d335b34f7daafc0d62f9ef6f1dfe2302e24471a] vs 62708377074826027686071360316569530966009902562575654183458172972917642219758 [0x8aa3af0374a9462120fd80217f7fc699b2d825a6ce31cb549c89e3ba431bd0ee])
  UVM_INFO @ 7809.679680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.62185113078855851952458442938025628168086580544227593431768187701667739901652
Line 466, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9908.960480 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (68438459122780316351263149299298614832380811352741911101525458115061089220212 [0x974ecb8f37c5f1e3a34a8d3712410dadaef6c7fa550c7efbe4b81b291eaeb674] vs 115561989410479383941513507258528827900861470187088762165853810264295768006626 [0xff7dc4a311fbc3e67d4829e3cc92d33411c0f6e3107f134827bf05c47ac31fe2])
  UVM_INFO @ 9908.960480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation_prod.62624121931197414662134675240944125566643545638526754144830146942424276697587
Line 476, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7251.455800 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (106064936546817142663882640781057318232937169577083107972397406675723152575250 [0xea7ea06e1e043c81405c390b3e90f3edb805aa64112e795a14e5ec8401dccb12] vs 105261829856437196423108643236855929495622816649103627326958417888602551675270 [0xe8b8159b5c70da32fd09226a80f3b47931aecc4c6d7c0ac9525bf95d21bee986])
  UVM_INFO @ 7251.455800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

Test chip_jtag_csr_rw has 3 failures.

0.chip_jtag_csr_rw.58627873805075255845149688049809642148660680014361508189836437684937976229450
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3406.737321 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h93d7dfac  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h0  a_user: 'h26930  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3406.737321 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_csr_rw.13489983723361163984598032826377706622027825034840678791104793173573094367187
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4772.040988 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h93aa4003  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h1  a_user: 'h248b9  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4772.040988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_jtag_mem_access has 3 failures.

0.chip_jtag_mem_access.24607287064970074132039751199609387910634684662554655608229698946613568269338
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3462.845106 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h2e355be2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h1  a_user: 'h248ce  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3462.845106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_mem_access.31310960230732774706257947145416054447729921365262575797410038614391473664517
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4779.611655 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h58e63c39  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h0  a_user: 'h26970  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4779.611655 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (sec_cm_pkg.sv:53) [sec_cm_pkg] find_sec_cm_if_proxy: no proxy with path *otp_ctrl.u_otp.*u_state_regs has 4 failures:
- Test chip_sw_all_escalation_resets has 4 failures.
  - 12.chip_sw_all_escalation_resets.106073396299202968619060707329497954927276610554467629789498906003925122577810
    Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.240001 us: (sec_cm_pkg.sv:53) [sec_cm_pkg] find_sec_cm_if_proxy: no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 19.chip_sw_all_escalation_resets.95997688238810265111922489682554815403265443205131053927617925211685145360750
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.100001 us: (sec_cm_pkg.sv:53) [sec_cm_pkg] find_sec_cm_if_proxy: no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_example_rom has 3 failures.
  - 0.chip_sw_example_rom.17462003387912877139486804240535197509089468792335379026225526106959607777426
    Line 633, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_example_rom.76558701926787130756097941495564125318213801115450629025743463329287368041517
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.100229206211322089486608578373344271212301769574390254476555580535518153237693
    Line 485, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4952.224876 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4952.224876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.33878747509288901105410919671302236565010338054035412902737763797208682870899
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5437.929680 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5437.929680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 3 failures:
- Test chip_sw_rstmgr_alert_info has 3 failures.
  - 0.chip_sw_rstmgr_alert_info.64348041151999317746800275541856492368529602417272058738997755848183930475687
    Line 705, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6404.637024 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6404.637024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rstmgr_alert_info.7029325633028886746972541764589962142036906671649207646964564247765078664595
    Line 656, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 11211.601156 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 11211.601156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 3 failures:

Test chip_sw_soc_proxy_external_alerts has 3 failures.

0.chip_sw_soc_proxy_external_alerts.64176654496138510325291794610307150700301711638660398888861712561520004411465
Line 457, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 5032.177180 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5032.177180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_soc_proxy_external_alerts.101391535332333785517328597197346415601427834162045601124061353637896378498578
Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 3769.454780 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3769.454780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
- Test chip_sw_soc_proxy_external_wakeup has 3 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.66314757143262096343752023265343537774569608384898477169764556290954685846936
    Line 503, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4617.578112 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4617.578112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_soc_proxy_external_wakeup.92136875428563063688543761659398693075801601481285874883456676181383728821757
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5396.441320 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5396.441320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 3 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.105149227848606129866465123904734622368582512885218219849605938173562096048155
    Line 513, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4492.063008 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4492.063008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aon_timer_wdog_bite_reset.109913911937434564940701870617735752084494745017430399184351303272052005018740
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5878.721668 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5878.721668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.25147030035822000399612574181278504851248805086814084590746011896032986496612
    Line 481, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5210.283824 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5210.283824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rv_core_ibex_nmi_irq.101124087157390816582555941060576962493832593788890096840426146176765788852462
    Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5823.050600 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5823.050600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_kmac_app_rom has 3 failures.
  - 0.chip_sw_kmac_app_rom.17006609451997383850177916428338084794367184008543740559113536770197582020682
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_app_rom.71641219084313806960310346155991006081161733754182944349231337046085157967626
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 3 failures:
- Test chip_rv_dm_ndm_reset_req has 3 failures.
  - 0.chip_rv_dm_ndm_reset_req.34517739422045297473970500294875604741264871898155769231172490978485464867613
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13539.233680 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13539.233680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_rv_dm_ndm_reset_req.18977364656299792970645152380152323335902445013010807509955448355189851875692
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15408.040360 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15408.040360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 3 failures:

Test chip_sw_dma_abort has 3 failures.

0.chip_sw_dma_abort.91239727563438881103834881281213860511706855785226596877679737783266984106256
Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 5472.015272 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5472.015272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_dma_abort.40776582242250299582852447707501766273796882943042633985074699563160400627443
Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 5558.325634 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5558.325634 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 2.chip_sw_all_escalation_resets.54903612530176381028940765169838849591872036856401792094373884779215814086106
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 4405.598896 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 4405.598896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.chip_sw_all_escalation_resets.22013916843242654394381134984768327577099626632324041366161835176001647549854
    Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 4194.336624 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 4194.336624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35908) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_tl_errors has 2 failures.

10.chip_tl_errors.15144783335261862540532630171418653392463648066615023252089069967714156457843
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4995.730542 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35908) { a_addr: 'h2210  a_data: 'hb7d02ddb  a_mask: 'he  a_size: 'h2  a_param: 'h0  a_source: 'hf8  a_opcode: 'h4  a_user: 'h27eb6  d_param: 'h0  d_source: 'hf8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4995.730542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.chip_tl_errors.64696555183217776261322952396314732933753213208275451416330237614958851171821
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4358.165852 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35908) { a_addr: 'h2210  a_data: 'h9e0b7214  a_mask: 'h5  a_size: 'h2  a_param: 'h0  a_source: 'h7f  a_opcode: 'h4  a_user: 'h2691a  d_param: 'h0  d_source: 'h7f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4358.165852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:

Test chip_sw_all_escalation_resets has 2 failures.

13.chip_sw_all_escalation_resets.52840306295440409092354578595920267108065483530279702883995229789876929915015
Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log

  UVM_ERROR @ 12010.160001 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.chip_sw_all_escalation_resets.51915297496909986158089704153422839293955038041141237588394085953752453222701
Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest/run.log

  UVM_ERROR @ 12010.180001 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36854) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures: