AES/MASKED Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: `f19c6a3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	10.000s	308.840us	1	1	100.00
V1	smoke	aes_smoke	7.000s	68.757us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	15.000s	206.899us	5	5	100.00
V1	csr_rw	aes_csr_rw	15.000s	67.477us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	18.000s	191.922us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	16.000s	155.812us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	15.000s	58.355us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	15.000s	67.477us	20	20	100.00
		aes_csr_aliasing	16.000s	155.812us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	68.757us	50	50	100.00
		aes_config_error	19.000s	2.592ms	50	50	100.00
		aes_stress	10.000s	224.446us	50	50	100.00
V2	key_length	aes_smoke	7.000s	68.757us	50	50	100.00
		aes_config_error	19.000s	2.592ms	50	50	100.00
		aes_stress	10.000s	224.446us	50	50	100.00
V2	back2back	aes_stress	10.000s	224.446us	50	50	100.00
		aes_b2b	30.000s	1.163ms	50	50	100.00
V2	backpressure	aes_stress	10.000s	224.446us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	68.757us	50	50	100.00
		aes_config_error	19.000s	2.592ms	50	50	100.00
		aes_stress	10.000s	224.446us	50	50	100.00
		aes_alert_reset	15.000s	879.241us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	293.277us	50	50	100.00
		aes_config_error	19.000s	2.592ms	50	50	100.00
		aes_alert_reset	15.000s	879.241us	50	50	100.00
V2	trigger_clear_test	aes_clear	12.000s	195.649us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	1.301ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	15.000s	879.241us	50	50	100.00
V2	stress	aes_stress	10.000s	224.446us	50	50	100.00
V2	sideload	aes_stress	10.000s	224.446us	50	50	100.00
		aes_sideload	24.000s	1.885ms	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	432.640us	50	50	100.00
V2	stress_all	aes_stress_all	1.117m	3.154ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	58.854us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	17.000s	413.141us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	17.000s	413.141us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	15.000s	206.899us	5	5	100.00
		aes_csr_rw	15.000s	67.477us	20	20	100.00
		aes_csr_aliasing	16.000s	155.812us	5	5	100.00
		aes_same_csr_outstanding	15.000s	61.186us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	15.000s	206.899us	5	5	100.00
		aes_csr_rw	15.000s	67.477us	20	20	100.00
		aes_csr_aliasing	16.000s	155.812us	5	5	100.00
		aes_same_csr_outstanding	15.000s	61.186us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	20.000s	2.170ms	50	50	100.00
V2S	fault_inject	aes_fi	27.000s	2.348ms	49	50	98.00
		aes_control_fi	56.000s	10.131ms	283	300	94.33
		aes_cipher_fi	44.000s	10.003ms	335	350	95.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	17.000s	500.654us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	17.000s	500.654us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	17.000s	500.654us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	17.000s	500.654us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	16.000s	120.072us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.458ms	5	5	100.00
		aes_tl_intg_err	17.000s	490.772us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	17.000s	490.772us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	15.000s	879.241us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	17.000s	500.654us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	68.757us	50	50	100.00
		aes_stress	10.000s	224.446us	50	50	100.00
		aes_alert_reset	15.000s	879.241us	50	50	100.00
		aes_core_fi	25.000s	10.006ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	17.000s	500.654us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	224.932us	50	50	100.00
		aes_stress	10.000s	224.446us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	224.446us	50	50	100.00
		aes_sideload	24.000s	1.885ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	224.932us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	224.932us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	224.932us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	224.932us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	224.932us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	224.446us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	224.446us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	27.000s	2.348ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	27.000s	2.348ms	49	50	98.00
		aes_control_fi	56.000s	10.131ms	283	300	94.33
		aes_cipher_fi	44.000s	10.003ms	335	350	95.71
		aes_ctr_fi	6.000s	94.952us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	27.000s	2.348ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	27.000s	2.348ms	49	50	98.00
		aes_control_fi	56.000s	10.131ms	283	300	94.33
		aes_cipher_fi	44.000s	10.003ms	335	350	95.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	44.000s	10.003ms	335	350	95.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	27.000s	2.348ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	27.000s	2.348ms	49	50	98.00
		aes_control_fi	56.000s	10.131ms	283	300	94.33
		aes_ctr_fi	6.000s	94.952us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	27.000s	2.348ms	49	50	98.00
		aes_control_fi	56.000s	10.131ms	283	300	94.33
		aes_cipher_fi	44.000s	10.003ms	335	350	95.71
		aes_ctr_fi	6.000s	94.952us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	15.000s	879.241us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	27.000s	2.348ms	49	50	98.00
		aes_control_fi	56.000s	10.131ms	283	300	94.33
		aes_cipher_fi	44.000s	10.003ms	335	350	95.71
		aes_ctr_fi	6.000s	94.952us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	27.000s	2.348ms	49	50	98.00
		aes_control_fi	56.000s	10.131ms	283	300	94.33
		aes_cipher_fi	44.000s	10.003ms	335	350	95.71
		aes_ctr_fi	6.000s	94.952us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	27.000s	2.348ms	49	50	98.00
		aes_control_fi	56.000s	10.131ms	283	300	94.33
		aes_ctr_fi	6.000s	94.952us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	27.000s	2.348ms	49	50	98.00
		aes_control_fi	56.000s	10.131ms	283	300	94.33
		aes_cipher_fi	44.000s	10.003ms	335	350	95.71
V2S		TOTAL			949	985	96.35
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	29.000s	995.914us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1556	1602	97.13

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.42	98.63	96.52	99.44	95.70	97.99	97.78	99.11	98.79

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_cipher_fi has 15 failures.
  - 29.aes_cipher_fi.103880271265403613517827773312080301335190487811041289769793890545562736427708
    Line 144, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10025115115 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025115115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 90.aes_cipher_fi.29767561405566252943493606198811698886404026047398752518453887888884539006996
    Line 143, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/90.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002652963 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002652963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 41.aes_control_fi.96678450698499270862934738327156737283300144585731178450087250284270322651012
    Line 140, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/41.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011969467 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011969467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 55.aes_control_fi.46628277626066281600050196116104542396241262665789862917801933898959221730895
    Line 145, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014175157 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014175157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
Job timed out after * minutes has 8 failures:
- Test aes_ctr_fi has 1 failures.
  - 9.aes_ctr_fi.91007459462716004051545826790183837732053950375277195288386163669398117693658
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_control_fi has 7 failures.
  - 50.aes_control_fi.108133684989068776968018141461400878449344130898200569145220998815051406323757
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/50.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 74.aes_control_fi.2923590838638636966530710591678237661132597423955635445833756065602429153560
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/74.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.49932014747942061914861737262881232544040710077154914547035128022389751634214
Line 365, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 995913900 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 995913900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.19304522285238493984658190491904122693879286252135897367258419114995678782085
Line 237, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 162143174 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 162143174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.29093340404048228210579437381327541744428236608702811383961435309971705036753
    Line 201, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 161114760 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 161114760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.58210484011685200025182380665705435755258796046655910887162675439608493662240
    Line 144, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 102007640 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 102007640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

1.aes_core_fi.66963703002638241625791852261200966493271184565821263611880093440460694384561
Line 134, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_core_fi/latest/run.log

  UVM_FATAL @ 10017859549 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017859549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

50.aes_core_fi.51642165790537615906855833903260991797048395467470409297116773939190691024729
Line 130, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/50.aes_core_fi/latest/run.log

  UVM_FATAL @ 10005686072 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005686072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 8.aes_stress_all_with_rand_reset.99172926052173251367649200452897849771772022013418367950936096840161086919088
    Line 132, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  10090226 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  10090226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.32689415778785055004005088409779096062159878781350751974006831801003578576351
    Line 225, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 160781050 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 160781050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 40.aes_fi.79648595553569214962350799250868085173175196512226285493436335470313196367926
    Line 37466, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/40.aes_fi/latest/run.log
```
  UVM_FATAL @  86435903 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  86435903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```