AES/UNMASKED Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: `f19c6a3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	93.348us	1	1	100.00
V1	smoke	aes_smoke	32.000s	117.571us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	76.715us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	86.292us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	195.081us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	1.087ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	102.465us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	86.292us	20	20	100.00
		aes_csr_aliasing	7.000s	1.087ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	32.000s	117.571us	50	50	100.00
		aes_config_error	32.000s	62.327us	50	50	100.00
		aes_stress	31.000s	71.992us	50	50	100.00
V2	key_length	aes_smoke	32.000s	117.571us	50	50	100.00
		aes_config_error	32.000s	62.327us	50	50	100.00
		aes_stress	31.000s	71.992us	50	50	100.00
V2	back2back	aes_stress	31.000s	71.992us	50	50	100.00
		aes_b2b	32.000s	197.574us	50	50	100.00
V2	backpressure	aes_stress	31.000s	71.992us	50	50	100.00
V2	multi_message	aes_smoke	32.000s	117.571us	50	50	100.00
		aes_config_error	32.000s	62.327us	50	50	100.00
		aes_stress	31.000s	71.992us	50	50	100.00
		aes_alert_reset	31.000s	138.108us	50	50	100.00
V2	failure_test	aes_man_cfg_err	32.000s	100.953us	50	50	100.00
		aes_config_error	32.000s	62.327us	50	50	100.00
		aes_alert_reset	31.000s	138.108us	50	50	100.00
V2	trigger_clear_test	aes_clear	32.000s	154.021us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	207.839us	1	1	100.00
V2	reset_recovery	aes_alert_reset	31.000s	138.108us	50	50	100.00
V2	stress	aes_stress	31.000s	71.992us	50	50	100.00
V2	sideload	aes_stress	31.000s	71.992us	50	50	100.00
		aes_sideload	31.000s	62.776us	50	50	100.00
V2	deinitialization	aes_deinit	32.000s	87.471us	50	50	100.00
V2	stress_all	aes_stress_all	41.000s	426.831us	10	10	100.00
V2	alert_test	aes_alert_test	31.000s	77.925us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	302.819us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	302.819us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	76.715us	5	5	100.00
		aes_csr_rw	5.000s	86.292us	20	20	100.00
		aes_csr_aliasing	7.000s	1.087ms	5	5	100.00
		aes_same_csr_outstanding	6.000s	804.326us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	76.715us	5	5	100.00
		aes_csr_rw	5.000s	86.292us	20	20	100.00
		aes_csr_aliasing	7.000s	1.087ms	5	5	100.00
		aes_same_csr_outstanding	6.000s	804.326us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	32.000s	344.147us	50	50	100.00
V2S	fault_inject	aes_fi	31.000s	67.853us	50	50	100.00
		aes_control_fi	31.000s	48.844us	275	300	91.67
		aes_cipher_fi	33.000s	10.003ms	335	350	95.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	133.580us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	133.580us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	133.580us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	133.580us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	206.688us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	33.000s	1.479ms	5	5	100.00
		aes_tl_intg_err	6.000s	556.524us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	556.524us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	31.000s	138.108us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	133.580us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	32.000s	117.571us	50	50	100.00
		aes_stress	31.000s	71.992us	50	50	100.00
		aes_alert_reset	31.000s	138.108us	50	50	100.00
		aes_core_fi	32.000s	10.007ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	133.580us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	31.000s	71.753us	50	50	100.00
		aes_stress	31.000s	71.992us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	31.000s	71.992us	50	50	100.00
		aes_sideload	31.000s	62.776us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	31.000s	71.753us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	31.000s	71.753us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	31.000s	71.753us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	31.000s	71.753us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	31.000s	71.753us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	31.000s	71.992us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	31.000s	71.992us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	31.000s	67.853us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	31.000s	67.853us	50	50	100.00
		aes_control_fi	31.000s	48.844us	275	300	91.67
		aes_cipher_fi	33.000s	10.003ms	335	350	95.71
		aes_ctr_fi	31.000s	69.146us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	31.000s	67.853us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	31.000s	67.853us	50	50	100.00
		aes_control_fi	31.000s	48.844us	275	300	91.67
		aes_cipher_fi	33.000s	10.003ms	335	350	95.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	33.000s	10.003ms	335	350	95.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	31.000s	67.853us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	31.000s	67.853us	50	50	100.00
		aes_control_fi	31.000s	48.844us	275	300	91.67
		aes_ctr_fi	31.000s	69.146us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	31.000s	67.853us	50	50	100.00
		aes_control_fi	31.000s	48.844us	275	300	91.67
		aes_cipher_fi	33.000s	10.003ms	335	350	95.71
		aes_ctr_fi	31.000s	69.146us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	31.000s	138.108us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	31.000s	67.853us	50	50	100.00
		aes_control_fi	31.000s	48.844us	275	300	91.67
		aes_cipher_fi	33.000s	10.003ms	335	350	95.71
		aes_ctr_fi	31.000s	69.146us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	31.000s	67.853us	50	50	100.00
		aes_control_fi	31.000s	48.844us	275	300	91.67
		aes_cipher_fi	33.000s	10.003ms	335	350	95.71
		aes_ctr_fi	31.000s	69.146us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	31.000s	67.853us	50	50	100.00
		aes_control_fi	31.000s	48.844us	275	300	91.67
		aes_ctr_fi	31.000s	69.146us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	31.000s	67.853us	50	50	100.00
		aes_control_fi	31.000s	48.844us	275	300	91.67
		aes_cipher_fi	33.000s	10.003ms	335	350	95.71
V2S		TOTAL			939	985	95.33
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	38.000s	487.040us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1546	1602	96.50

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.44	97.78	95.01	98.84	93.89	97.99	93.33	98.85	98.19

Failure Buckets

Job timed out after * minutes has 27 failures:
- Test aes_control_fi has 18 failures.
  - 26.aes_control_fi.98960857082780712125179006379038873326386164558846739952115171460841478249044
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 30.aes_control_fi.33444770780215583140531062816411956291219293860761003970645109934785913499051
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 16 more failures.
- Test aes_ctr_fi has 1 failures.
  - 27.aes_ctr_fi.16388206094353411348842051592656157837244368380697414679114150562131739451501
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/27.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_cipher_fi has 8 failures.
  - 34.aes_cipher_fi.23890555189200541386728457155120180305102269177600618239624998695636220757596
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/34.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 71.aes_cipher_fi.14279968442343752395742876515306317831902663244612127488777897422044187655419
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/71.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.35586918589975835051639470966601522818261297291478390727964750683063408160943
Line 450, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4019234708 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4019234708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.20326332628864454871589511715124244684699820831850024864415916837906742781726
Line 236, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2575529020 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2575529020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 8.aes_cipher_fi.19428761548408880439140534415911333010029411541443265357327865905367893582260
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006387298 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006387298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_cipher_fi.92468171369296152657582952939661441193528491771865017044248994344158706336056
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005406272 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005406272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 48.aes_control_fi.15914452732824463434563354231520626988695138884443694623067365939065994142952
    Line 142, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/48.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007377147 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007377147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 125.aes_control_fi.115678645369358865269546000156947054600448494464467132188361729031044488641064
    Line 136, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/125.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011842740 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011842740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 51.aes_core_fi.29431931371506182766926352729406960830775840483208630246939814989812288102183
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/51.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006564269 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006564269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 59.aes_core_fi.6387472504650140548805312253096460715081033881393758429521621099136811683768
    Line 142, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/59.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004051505 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004051505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.58738422049484784131731556855100040015435896784445151061040771468416117083384
    Line 198, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 185469207 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 185469207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.31709177104099279660943125771561070300572293340052459019077736612015551728804
    Line 1497, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 487039754 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 487039754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 28.aes_core_fi.92149800785931923318806730701889702824059086368677328197991533654676456771232
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/28.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10053320498 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10053320498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```