CSRNG Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: `f19c6a3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	112.310us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	38.131us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	253.507us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	21.000s	1.086ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	164.096us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	21.763us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	253.507us	20	20	100.00
		csrng_csr_aliasing	9.000s	164.096us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	20.000s	1.132ms	198	200	99.00
V2	alerts	csrng_alert	51.000s	4.598ms	500	500	100.00
V2	err	csrng_err	7.000s	44.647us	500	500	100.00
V2	cmds	csrng_cmds	8.400m	39.239ms	50	50	100.00
V2	life cycle	csrng_cmds	8.400m	39.239ms	50	50	100.00
V2	stress_all	csrng_stress_all	17.133m	81.556ms	45	50	90.00
V2	intr_test	csrng_intr_test	6.000s	49.050us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	232.706us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	17.000s	1.077ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	17.000s	1.077ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	38.131us	5	5	100.00
		csrng_csr_rw	8.000s	253.507us	20	20	100.00
		csrng_csr_aliasing	9.000s	164.096us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	295.013us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	38.131us	5	5	100.00
		csrng_csr_rw	8.000s	253.507us	20	20	100.00
		csrng_csr_aliasing	9.000s	164.096us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	295.013us	20	20	100.00
V2		TOTAL			1433	1440	99.51
V2S	tl_intg_err	csrng_sec_cm	8.000s	261.034us	5	5	100.00
		csrng_tl_intg_err	19.000s	1.300ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	41.510us	50	50	100.00
		csrng_csr_rw	8.000s	253.507us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	51.000s	4.598ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	17.133m	81.556ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
		csrng_sec_cm	8.000s	261.034us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
		csrng_sec_cm	8.000s	261.034us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
		csrng_sec_cm	8.000s	261.034us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
		csrng_sec_cm	8.000s	261.034us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
		csrng_sec_cm	8.000s	261.034us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
		csrng_sec_cm	8.000s	261.034us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
		csrng_sec_cm	8.000s	261.034us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	51.000s	4.598ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	17.133m	81.556ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	51.000s	4.598ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	19.000s	1.300ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
		csrng_sec_cm	8.000s	261.034us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
		csrng_sec_cm	8.000s	261.034us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	20.000s	1.132ms	198	200	99.00
		csrng_err	7.000s	44.647us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.317m	2.566ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1613	1630	98.96

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.76	98.63	96.68	99.97	97.42	92.08	100.00	97.36	90.57

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 0.csrng_stress_all_with_rand_reset.5298231544372658874458470149951544664651981307366490419456928299067754080500
    Line 99, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108029911 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 108029911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.96300788039661022850312841641040178708425743747088469717913158286189700708953
    Line 103, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 450659257 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 450659257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 5 failures:

Test csrng_stress_all has 5 failures.

22.csrng_stress_all.85676292295914021237004065497033692520536815861849007115790563485618338214779
Line 151, in log /nightly/runs/scratch/master/csrng-sim-xcelium/22.csrng_stress_all/latest/run.log

  UVM_ERROR @ 18807254859 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 18807254859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.csrng_stress_all.1914488105576862541245716344358251511525846698543673283152766023305848454516
Line 153, in log /nightly/runs/scratch/master/csrng-sim-xcelium/26.csrng_stress_all/latest/run.log

  UVM_ERROR @ 14373951060 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 14373951060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 2 failures:

Test csrng_intr has 2 failures.

96.csrng_intr.29713941049939101616289663205340525585842482275445934263577811284145948283988
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/96.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 82786773 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  82786773 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  82786773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

130.csrng_intr.58961999530039236300861293429557444277835719137033035152391536526842142153214
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/130.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 117938105 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 117938105 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 117938105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 9.csrng_stress_all_with_rand_reset.14683598543777484191161457910058886179390435823366539816498983987564184463251
    Line 107, in log /nightly/runs/scratch/master/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   9247524 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @   9247524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```