DMA Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: f19c6a3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	12.000s	410.316us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	13.000s	1.798ms	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	12.000s	1.567ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	30.538us	5	5	100.00
V1	csr_rw	dma_csr_rw	5.000s	158.411us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	15.000s	7.079ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	10.000s	2.682ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	20.127us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	158.411us	20	20	100.00
		dma_csr_aliasing	10.000s	2.682ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.717m	27.836ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	25.567m	141.738ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	41.900m	216.814ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	5.483m	388.663ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	25.567m	141.738ms	3	3	100.00
V2	dma_abort	dma_abort	22.000s	1.199ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	3.533m	34.147ms	3	3	100.00
V2	intr_test	dma_intr_test	5.000s	15.609us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	7.000s	714.241us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	7.000s	714.241us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	30.538us	5	5	100.00
		dma_csr_rw	5.000s	158.411us	20	20	100.00
		dma_csr_aliasing	10.000s	2.682ms	5	5	100.00
		dma_same_csr_outstanding	6.000s	290.586us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	30.538us	5	5	100.00
		dma_csr_rw	5.000s	158.411us	20	20	100.00
		dma_csr_aliasing	10.000s	2.682ms	5	5	100.00
		dma_same_csr_outstanding	6.000s	290.586us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	28.000s	204.399us	5	5	100.00
		dma_generic_stress	5.483m	388.663ms	5	5	100.00
		dma_handshake_stress	25.567m	141.738ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	8.000s	1.018ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	1.983m	12.493ms	5	5	100.00
		dma_longer_transfer	14.000s	709.646us	5	5	100.00
		TOTAL			304	304	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
75.43	96.97	95.19	96.93	96.02	82.72	82.76	97.77	40.58