EDN Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: f19c6a3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.660s 16.593us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.970s 48.831us 5 5 100.00
V1 csr_rw edn_csr_rw 2.380s 29.702us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.830s 2.773ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.800s 48.728us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.700s 35.833us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.380s 29.702us 20 20 100.00
edn_csr_aliasing 2.800s 48.728us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 4.990s 158.758us 300 300 100.00
V2 csrng_commands edn_genbits 4.990s 158.758us 300 300 100.00
V2 genbits edn_genbits 4.990s 158.758us 300 300 100.00
V2 interrupts edn_intr 2.710s 21.602us 50 50 100.00
V2 alerts edn_alert 3.070s 325.366us 200 200 100.00
V2 errs edn_err 2.660s 79.978us 100 100 100.00
V2 disable edn_disable 2.430s 16.760us 50 50 100.00
edn_disable_auto_req_mode 2.940s 43.200us 50 50 100.00
V2 stress_all edn_stress_all 7.900s 545.441us 50 50 100.00
V2 intr_test edn_intr_test 2.390s 10.921us 50 50 100.00
V2 alert_test edn_alert_test 2.620s 19.112us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.790s 235.593us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.790s 235.593us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.970s 48.831us 5 5 100.00
edn_csr_rw 2.380s 29.702us 20 20 100.00
edn_csr_aliasing 2.800s 48.728us 5 5 100.00
edn_same_csr_outstanding 2.560s 28.718us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.970s 48.831us 5 5 100.00
edn_csr_rw 2.380s 29.702us 20 20 100.00
edn_csr_aliasing 2.800s 48.728us 5 5 100.00
edn_same_csr_outstanding 2.560s 28.718us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.830s 1.350ms 5 5 100.00
edn_tl_intg_err 29.620s 3.468ms 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.450s 33.331us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 3.070s 325.366us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.830s 1.350ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.830s 1.350ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.830s 1.350ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.830s 1.350ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 3.070s 325.366us 200 200 100.00
edn_sec_cm 8.830s 1.350ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 3.070s 325.366us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 29.620s 3.468ms 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.745m 5.328ms 27 50 54.00
V3 TOTAL 27 50 54.00
TOTAL 1107 1130 97.96

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.70 98.32 94.17 97.07 91.28 96.33 99.78 92.94

Failure Buckets