HMAC Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: f19c6a3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.170s	5.106ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.250s	38.785us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.400s	19.008us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	12.950s	326.097us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.020s	2.148ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	18.160m	535.928ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.400s	19.008us	20	20	100.00
		hmac_csr_aliasing	7.020s	2.148ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.956m	27.824ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.424m	6.182ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.205m	13.812ms	30	30	100.00
		hmac_test_sha384_vectors	9.417m	28.312ms	75	75	100.00
		hmac_test_sha512_vectors	8.576m	74.756ms	75	75	100.00
		hmac_test_hmac256_vectors	15.750s	320.990us	50	50	100.00
		hmac_test_hmac384_vectors	17.170s	1.463ms	60	60	100.00
		hmac_test_hmac512_vectors	19.830s	362.776us	75	75	100.00
V2	burst_wr	hmac_burst_wr	39.280s	3.761ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	22.358m	10.503ms	10	10	100.00
V2	error	hmac_error	1.409m	28.261ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.863m	3.017ms	10	10	100.00
V2	save_and_restore	hmac_smoke	16.170s	5.106ms	10	10	100.00
		hmac_long_msg	1.956m	27.824ms	10	10	100.00
		hmac_back_pressure	1.424m	6.182ms	25	25	100.00
		hmac_datapath_stress	22.358m	10.503ms	10	10	100.00
		hmac_burst_wr	39.280s	3.761ms	50	50	100.00
		hmac_stress_all	46.211m	16.682ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.170s	5.106ms	10	10	100.00
		hmac_long_msg	1.956m	27.824ms	10	10	100.00
		hmac_back_pressure	1.424m	6.182ms	25	25	100.00
		hmac_datapath_stress	22.358m	10.503ms	10	10	100.00
		hmac_wipe_secret	1.863m	3.017ms	10	10	100.00
		hmac_test_sha256_vectors	4.205m	13.812ms	30	30	100.00
		hmac_test_sha384_vectors	9.417m	28.312ms	75	75	100.00
		hmac_test_sha512_vectors	8.576m	74.756ms	75	75	100.00
		hmac_test_hmac256_vectors	15.750s	320.990us	50	50	100.00
		hmac_test_hmac384_vectors	17.170s	1.463ms	60	60	100.00
		hmac_test_hmac512_vectors	19.830s	362.776us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.170s	5.106ms	10	10	100.00
		hmac_long_msg	1.956m	27.824ms	10	10	100.00
		hmac_back_pressure	1.424m	6.182ms	25	25	100.00
		hmac_datapath_stress	22.358m	10.503ms	10	10	100.00
		hmac_burst_wr	39.280s	3.761ms	50	50	100.00
		hmac_error	1.409m	28.261ms	10	10	100.00
		hmac_wipe_secret	1.863m	3.017ms	10	10	100.00
		hmac_test_sha256_vectors	4.205m	13.812ms	30	30	100.00
		hmac_test_sha384_vectors	9.417m	28.312ms	75	75	100.00
		hmac_test_sha512_vectors	8.576m	74.756ms	75	75	100.00
		hmac_test_hmac256_vectors	15.750s	320.990us	50	50	100.00
		hmac_test_hmac384_vectors	17.170s	1.463ms	60	60	100.00
		hmac_test_hmac512_vectors	19.830s	362.776us	75	75	100.00
		hmac_stress_all	46.211m	16.682ms	50	50	100.00
V2	stress_all	hmac_stress_all	46.211m	16.682ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.090s	12.126us	50	50	100.00
V2	intr_test	hmac_intr_test	2.170s	16.910us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.720s	796.647us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.720s	796.647us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.250s	38.785us	5	5	100.00
		hmac_csr_rw	2.400s	19.008us	20	20	100.00
		hmac_csr_aliasing	7.020s	2.148ms	5	5	100.00
		hmac_same_csr_outstanding	4.040s	597.017us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.250s	38.785us	5	5	100.00
		hmac_csr_rw	2.400s	19.008us	20	20	100.00
		hmac_csr_aliasing	7.020s	2.148ms	5	5	100.00
		hmac_same_csr_outstanding	4.040s	597.017us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.560s	471.276us	5	5	100.00
		hmac_tl_intg_err	5.160s	2.462ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.160s	2.462ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.170s	5.106ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	8.610s	129.270us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	5.587m	11.852ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	3.250s	1.125ms	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.04	100.00	97.20	100.00	100.00	100.00	99.76	47.30