I2C Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: `f19c6a3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.613m	9.957ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	30.490s	7.879ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.200s	22.281us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.340s	264.937us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.500s	707.356us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.080s	93.765us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.460s	153.704us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.340s	264.937us	20	20	100.00
		i2c_csr_aliasing	3.080s	93.765us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	9.530s	308.032us	49	50	98.00
V2	host_stress_all	i2c_host_stress_all	42.781m	41.910ms	18	50	36.00
V2	host_maxperf	i2c_host_perf	24.337m	98.847ms	49	50	98.00
V2	host_override	i2c_host_override	2.250s	43.761us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.986m	5.218ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.883m	42.190ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.880s	474.403us	50	50	100.00
		i2c_host_fifo_fmt_empty	24.400s	2.241ms	50	50	100.00
		i2c_host_fifo_reset_rx	14.010s	230.986us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.980m	13.722ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	52.480s	2.242ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	7.740s	181.512us	17	50	34.00
V2	target_glitch	i2c_target_glitch	13.920s	2.048ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	21.212m	63.239ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	10.100s	2.095ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.162m	19.999ms	50	50	100.00
		i2c_target_intr_smoke	11.290s	1.524ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.500s	298.569us	50	50	100.00
		i2c_target_fifo_reset_tx	3.360s	275.506us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	9.759m	49.948ms	50	50	100.00
		i2c_target_stress_rd	1.162m	19.999ms	50	50	100.00
		i2c_target_intr_stress_wr	6.840m	22.211ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	11.550s	6.009ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	3.050m	5.872ms	48	50	96.00
V2	bad_address	i2c_target_bad_addr	9.920s	7.319ms	47	50	94.00
V2	target_mode_glitch	i2c_target_hrst	46.110s	10.173ms	29	50	58.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.830s	699.573us	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.240s	637.155us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	24.337m	98.847ms	49	50	98.00
		i2c_host_perf_precise	24.211m	600.000ms	49	50	98.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	52.480s	2.242ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	12.360s	771.279us	49	50	98.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.180s	608.048us	50	50	100.00
		i2c_target_nack_acqfull_addr	5.430s	2.451ms	50	50	100.00
		i2c_target_nack_txstretch	3.440s	842.687us	37	50	74.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	24.070s	1.194ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.790s	578.742us	50	50	100.00
V2	alert_test	i2c_alert_test	2.140s	21.876us	50	50	100.00
V2	intr_test	i2c_intr_test	2.210s	26.576us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	4.110s	600.688us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	4.110s	600.688us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.200s	22.281us	5	5	100.00
		i2c_csr_rw	2.340s	264.937us	20	20	100.00
		i2c_csr_aliasing	3.080s	93.765us	5	5	100.00
		i2c_same_csr_outstanding	2.790s	54.366us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.200s	22.281us	5	5	100.00
		i2c_csr_rw	2.340s	264.937us	20	20	100.00
		i2c_csr_aliasing	3.080s	93.765us	5	5	100.00
		i2c_same_csr_outstanding	2.790s	54.366us	19	20	95.00
V2		TOTAL			1682	1792	93.86
V2S	tl_intg_err	i2c_tl_intg_err	3.590s	130.661us	20	20	100.00
		i2c_sec_cm	2.630s	71.863us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.590s	130.661us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	23.740s	11.282ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	4.630s	2.719ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	44.460s	8.035ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1862	2042	91.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.00	97.25	89.78	74.17	72.02	94.18	98.52	90.06

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 38 failures:

Test i2c_host_stress_all has 22 failures.

0.i2c_host_stress_all.7983690570308073754127828687625694382421042001085370971143736704434738274735
Line 206, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 20873691042 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2262314

2.i2c_host_stress_all.86905358838999263301428091337716433545066671968298247885422755091620306520144
Line 197, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 48029010795 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3388834

... and 20 more failures.

Test i2c_host_mode_toggle has 16 failures.

0.i2c_host_mode_toggle.101631624186286555597473537952291090261008101757403709004505604847823566765400
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 722030790 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @42605

4.i2c_host_mode_toggle.68305763482738212703781123436791081090338647660666274474063956016269727029311
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 113365737 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @83881

... and 14 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 25 failures:
- Test i2c_target_unexp_stop has 24 failures.
  - 0.i2c_target_unexp_stop.82299697874422936209197096743362385997275472157094097156920876192586776108954
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 387755946 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 168 [0xa8])
  UVM_INFO @ 387755946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.65590622030537737800505300558915479557121834927666450716644760914745640323055
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  76987320 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 160 [0xa0])
  UVM_INFO @  76987320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 22 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 4.i2c_target_stress_all_with_rand_reset.69029114503426440895653185026366186149747217906209373364838162874863044477042
    Line 96, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 637595527 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 123 [0x7b])
  UVM_INFO @ 637595527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 21 failures:
- Test i2c_target_hrst has 21 failures.
  - 0.i2c_target_hrst.96235685050141769714173743175771349783274490502093931009467519635583696855651
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10173438756 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10173438756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_hrst.75585179995407694930683162483157206772843813731987548489724602841525421926243
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10231968416 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10231968416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 19 failures:
- Test i2c_target_unexp_stop has 19 failures.
  - 3.i2c_target_unexp_stop.56331444284849238532589550847716092272830165149556754531059683307385712746488
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1692715830 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1692715830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_unexp_stop.20540910302433283787091098671068226244294825716359946945868289563659356955940
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 181510260 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 181510260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.23451117411489135220636024507119859894216310459651497261146348941226798764500
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10673886906 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10673886906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.78943041460355828435362235040152565121871785324568191146852785914870721172247
Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1050960564 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1050960564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 5 failures.

1.i2c_target_stress_all_with_rand_reset.92070292504864131862846261975203794428179235451586656825939677124165581713580
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 310897752 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 310897752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.31520234566509021543867107517000398707126837627069585845436152094841222150988
Line 96, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1804259810 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1804259810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 13 failures:
- Test i2c_target_nack_txstretch has 13 failures.
  - 1.i2c_target_nack_txstretch.60413697048198572645398077852452446061710932837658753692128608615141357784239
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 816608003 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 816608003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_nack_txstretch.7093907609110701665161161026557958557549704148325216400915691018161345593335
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 171121480 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 171121480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:

Test i2c_host_mode_toggle has 13 failures.

13.i2c_host_mode_toggle.74014951346351273465998985258904100370117265660350571007477266832911450906698
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 127496999 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

25.i2c_host_mode_toggle.11070758277337586376184222724733604554090534583835993077992834147307795477383
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/25.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 411339414 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 11 more failures.

Job timed out after * minutes has 9 failures:
- Test i2c_host_stress_all has 6 failures.
  - 4.i2c_host_stress_all.101467076775798108294535644217153136401763684485520099985965527271091792313289
    Log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 13.i2c_host_stress_all.17500879523354850826570761530856479822913545519606539837356703710679390495729
    Log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 4 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 9.i2c_target_stress_all_with_rand_reset.23261078519081475596408522678185970281945659505071124907224554593965939058710
    Log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 20 minutes
```
- Test i2c_host_perf has 1 failures.
  - 36.i2c_host_perf.40262768024232713831170829279256317598157920078303743241188007517731723411088
    Log /nightly/runs/scratch/master/i2c-sim-vcs/36.i2c_host_perf/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_error_intr has 1 failures.
  - 47.i2c_host_error_intr.13269389057285463151193078223888902058491878613009532043065289016755288737656
    Log /nightly/runs/scratch/master/i2c-sim-vcs/47.i2c_host_error_intr/latest/run.log
```
  Job timed out after 60 minutes
```

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:

Test i2c_target_unexp_stop has 7 failures.

15.i2c_target_unexp_stop.95892648360956158069808338356312199113358538696087603085548445778274686944872
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @  55858900 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @  55858900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.i2c_target_unexp_stop.12497677113604487164270213235604281336906834209036847976936644130220181714823
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 217250046 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 217250046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:

Test i2c_host_stress_all has 4 failures.

8.i2c_host_stress_all.16587635743243571786974846996918387742466499383927756377783492580236194766664
Line 213, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 67748247666 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @15924022

24.i2c_host_stress_all.86007492930188885028135923866714267498339719135429606835585678698616402390241
Line 180, in log /nightly/runs/scratch/master/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 170533172154 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @9214094

... and 2 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test i2c_host_perf_precise has 1 failures.
  - 17.i2c_host_perf_precise.5048082649679085566751839299863638183235035049855538277057337553076005921050
    Line 75, in log /nightly/runs/scratch/master/i2c-sim-vcs/17.i2c_host_perf_precise/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_bad_addr has 3 failures.
  - 20.i2c_target_bad_addr.7808211524528916850203216709504502829680534754245694102605591410409177585926
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/20.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 22.i2c_target_bad_addr.106255424957679407505898342903651626026976645231686648212209820743327447043602
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/22.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
- Test i2c_host_mode_toggle has 4 failures.
  - 18.i2c_host_mode_toggle.100388160519771000676992260405443138198666352137249879199249030185887771715300
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  22797634 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x70157e14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  22797634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 27.i2c_host_mode_toggle.108487542438486222552413209474518914215621168621001010430664741522385075663773
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/27.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 140792568 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x38670314, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 140792568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 0.i2c_target_stress_all_with_rand_reset.32822086722150903337215192272347813324046047799482020400604639865257391676731
    Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3923008089 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3923008089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_stress_all_with_rand_reset.22630405891327585994338157945693273985823324546332675821038377104166040562153
    Line 97, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1080980599 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1080980599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 2 failures:
- Test i2c_target_stretch has 2 failures.
  - 18.i2c_target_stretch.44236831875298234365174949543695232201309858967252628743743950637269626519510
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10047814695 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10047814695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 29.i2c_target_stretch.56892221208765967454129702043720736425273509427383980899311969073189800674927
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/29.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10005311777 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10005311777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
- Test i2c_target_tx_stretch_ctrl has 1 failures.
  - 32.i2c_target_tx_stretch_ctrl.75519444750896939028397757159043244485810219831273139232915091747607933605682
    Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/32.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 49.i2c_target_fifo_watermarks_tx.649248873332911191896808520916509050441757594060216658667019636836729517259
    Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_ERROR (cip_base_vseq.sv:525) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 5.i2c_same_csr_outstanding.87089492813437244128269866925605242753059055504873242430451317852984616991197
    Line 72, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  57029483 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  57029483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```