KEYMGR Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: `f19c6a3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	26.870s	1.493ms	50	50	100.00
V1	random	keymgr_random	48.620s	6.764ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.840s	105.717us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.600s	99.738us	18	20	90.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.680s	476.896us	3	5	60.00
V1	csr_aliasing	keymgr_csr_aliasing	11.170s	723.828us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.390s	28.631us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.600s	99.738us	18	20	90.00
		keymgr_csr_aliasing	11.170s	723.828us	4	5	80.00
V1		TOTAL			148	155	95.48
V2	cfgen_during_op	keymgr_cfg_regwen	54.030s	8.326ms	49	50	98.00
V2	sideload	keymgr_sideload	33.250s	1.693ms	50	50	100.00
		keymgr_sideload_kmac	1.132m	28.667ms	50	50	100.00
		keymgr_sideload_aes	34.220s	1.767ms	50	50	100.00
		keymgr_sideload_otbn	36.790s	1.531ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	18.450s	1.266ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	19.210s	455.403us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	13.490s	629.346us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	37.960s	1.628ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	47.480s	4.800ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	30.600s	4.763ms	50	50	100.00
V2	stress_all	keymgr_stress_all	2.433m	8.350ms	45	50	90.00
V2	intr_test	keymgr_intr_test	2.250s	13.351us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.320s	18.288us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.630s	220.413us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.630s	220.413us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.840s	105.717us	5	5	100.00
		keymgr_csr_rw	2.600s	99.738us	18	20	90.00
		keymgr_csr_aliasing	11.170s	723.828us	4	5	80.00
		keymgr_same_csr_outstanding	4.210s	1.589ms	16	20	80.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.840s	105.717us	5	5	100.00
		keymgr_csr_rw	2.600s	99.738us	18	20	90.00
		keymgr_csr_aliasing	11.170s	723.828us	4	5	80.00
		keymgr_same_csr_outstanding	4.210s	1.589ms	16	20	80.00
V2		TOTAL			730	740	98.65
V2S	sec_cm_additional_check	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
		keymgr_tl_intg_err	6.840s	912.680us	13	20	65.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.220s	259.831us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.220s	259.831us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.220s	259.831us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.220s	259.831us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	10.340s	654.303us	15	20	75.00
V2S	prim_count_check	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	6.840s	912.680us	13	20	65.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.220s	259.831us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	54.030s	8.326ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	48.620s	6.764ms	50	50	100.00
		keymgr_csr_rw	2.600s	99.738us	18	20	90.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	48.620s	6.764ms	50	50	100.00
		keymgr_csr_rw	2.600s	99.738us	18	20	90.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	48.620s	6.764ms	50	50	100.00
		keymgr_csr_rw	2.600s	99.738us	18	20	90.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	19.210s	455.403us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	47.480s	4.800ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	47.480s	4.800ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	48.620s	6.764ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	36.050s	2.887ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	23.490s	10.307ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	19.210s	455.403us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	23.490s	10.307ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	23.490s	10.307ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	23.490s	10.307ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.540s	1.276ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	23.490s	10.307ms	49	50	98.00
V2S		TOTAL			152	165	92.12
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.820s	2.763ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1063	1110	95.77

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.48	99.06	98.11	98.65	97.67	99.01	98.63	91.21

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 23 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 5 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.47583560282747882945940327780617080894146394956324022768778396560136053605709
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @  39276049 ps: (keymgr_csr_assert_fpv.sv:394) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @  39276049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.keymgr_shadow_reg_errors_with_csr_rw.59574410142226613019262298289095493718665483958035944455586003382299578610019
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @  39926582 ps: (keymgr_csr_assert_fpv.sv:444) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @  39926582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_rw has 2 failures.

0.keymgr_csr_rw.51318994403386715226841019893452478937679726615536086282413726418473257036453
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @  25471626 ps: (keymgr_csr_assert_fpv.sv:429) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @  25471626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_csr_rw.56796648747137669930960344136023932721194802631257112239371289546310207984852
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @  17519266 ps: (keymgr_csr_assert_fpv.sv:394) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @  17519266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_bit_bash has 2 failures.

0.keymgr_csr_bit_bash.30525497127453969223862490502589915197285337934137145472271897230116435144351
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @ 476896020 ps: (keymgr_csr_assert_fpv.sv:424) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @ 476896020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_csr_bit_bash.106933720631099636350044405317840283173493943389421644139886415544316793297524
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @ 531046838 ps: (keymgr_csr_assert_fpv.sv:444) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @ 531046838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_same_csr_outstanding has 4 failures.

0.keymgr_same_csr_outstanding.66834898462626172700938444482022296933234602752334746574981066062837539586710
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @ 172413765 ps: (keymgr_csr_assert_fpv.sv:454) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @ 172413765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.keymgr_same_csr_outstanding.76184744093350756591527891303840638112069118779924419250621062218252649021959
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @ 220405421 ps: (keymgr_csr_assert_fpv.sv:404) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @ 220405421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test keymgr_tl_intg_err has 7 failures.

1.keymgr_tl_intg_err.6167853575558838438848717788425264316725385844129848927764075923031088025991
Line 117, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @ 138962116 ps: (keymgr_csr_assert_fpv.sv:409) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @ 138962116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_tl_intg_err.28497420793685373733823412368402865291352649347243039208766552783028180751622
Line 85, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @  31966533 ps: (keymgr_csr_assert_fpv.sv:434) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @  31966533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

... and 2 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test keymgr_stress_all_with_rand_reset has 17 failures.
  - 1.keymgr_stress_all_with_rand_reset.106499010527360726054141644874712553919750086051137092791679599930151825185907
    Line 223, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 654484500 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 654484500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.keymgr_stress_all_with_rand_reset.94956220353510349008364163427444467291191474865934729817353603238678509243556
    Line 194, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1508647123 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1508647123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.
UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:
- Test keymgr_stress_all has 4 failures.
  - 3.keymgr_stress_all.106050741582318654536811175892084852232468174870276982672907898274034082494937
    Line 254, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 147233989 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 147233989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 17.keymgr_stress_all.44272858569473206337696113676780347884331773850693087939554891390796624679195
    Line 1811, in log /nightly/runs/scratch/master/keymgr-sim-vcs/17.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1109899843 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 1109899843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 8.keymgr_cfg_regwen.10560020824748234586603443608767703184643288624232162951651846584807129170242
    Line 134, in log /nightly/runs/scratch/master/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @   9861944 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @   9861944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 34.keymgr_stress_all.110975866075571189299836954102899442638588687984353052786722146912902690893390
    Line 1510, in log /nightly/runs/scratch/master/keymgr-sim-vcs/34.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 228066682 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_4
  UVM_INFO @ 228066682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (keymgr_custom_cm_vseq.sv:45) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 37.keymgr_custom_cm.33861272305340558445772807169179469956268672771609208179647130662844255640535
    Line 122, in log /nightly/runs/scratch/master/keymgr-sim-vcs/37.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 10306785375 ps: (keymgr_custom_cm_vseq.sv:45) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
  UVM_INFO @ 10306785375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```