KMAC/MASKED Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: `f19c6a3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.540m	5.512ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.500s	23.480us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.350s	91.146us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.190s	5.513ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.180s	384.365us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.680s	345.703us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.350s	91.146us	20	20	100.00
		kmac_csr_aliasing	8.180s	384.365us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.360s	28.259us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	3.000s	151.345us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.023h	268.449ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.630m	15.260ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.274m	368.061ms	5	5	100.00
		kmac_test_vectors_sha3_256	38.894m	93.814ms	5	5	100.00
		kmac_test_vectors_sha3_384	26.647m	83.421ms	5	5	100.00
		kmac_test_vectors_sha3_512	24.510s	1.326ms	5	5	100.00
		kmac_test_vectors_shake_128	41.409m	769.376ms	5	5	100.00
		kmac_test_vectors_shake_256	30.626m	323.413ms	5	5	100.00
		kmac_test_vectors_kmac	4.800s	234.156us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.270s	152.074us	5	5	100.00
V2	sideload	kmac_sideload	7.888m	72.396ms	50	50	100.00
V2	app	kmac_app	7.151m	67.289ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.942m	20.385ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	9.473m	308.999ms	50	50	100.00
V2	error	kmac_error	7.695m	24.285ms	50	50	100.00
V2	key_error	kmac_key_error	18.910s	6.819ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.650s	1.302ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.130s	905.978us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	15.880s	1.544ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.236m	11.538ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	53.600s	3.202ms	50	50	100.00
V2	stress_all	kmac_stress_all	36.778m	27.669ms	48	50	96.00
V2	intr_test	kmac_intr_test	2.420s	37.803us	50	50	100.00
V2	alert_test	kmac_alert_test	2.330s	27.181us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.330s	268.802us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.330s	268.802us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.500s	23.480us	5	5	100.00
		kmac_csr_rw	2.350s	91.146us	20	20	100.00
		kmac_csr_aliasing	8.180s	384.365us	5	5	100.00
		kmac_same_csr_outstanding	3.850s	426.499us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.500s	23.480us	5	5	100.00
		kmac_csr_rw	2.350s	91.146us	20	20	100.00
		kmac_csr_aliasing	8.180s	384.365us	5	5	100.00
		kmac_same_csr_outstanding	3.850s	426.499us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.490s	202.546us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.490s	202.546us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.490s	202.546us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.490s	202.546us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.650s	1.482ms	11	20	55.00
V2S	tl_intg_err	kmac_sec_cm	1.803m	27.247ms	5	5	100.00
		kmac_tl_intg_err	5.470s	4.350ms	16	20	80.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.470s	4.350ms	16	20	80.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	53.600s	3.202ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.540m	5.512ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.888m	72.396ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.490s	202.546us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.803m	27.247ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.803m	27.247ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.803m	27.247ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.540m	5.512ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	53.600s	3.202ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.803m	27.247ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.521m	13.362ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.540m	5.512ms	50	50	100.00
V2S		TOTAL			62	75	82.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.539m	3.733ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			920	940	97.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.32	99.09	94.50	99.89	79.58	97.09	99.37	97.72

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 12 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 8 failures.

0.kmac_shadow_reg_errors_with_csr_rw.67240545984079459856143768773447543415534006331517394593667351393718725862070
Line 81, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  47334287 ps: (kmac_csr_assert_fpv.sv:535) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  47334287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_shadow_reg_errors_with_csr_rw.65150268501609040019437212105233801840076419004703202018491018867265369842497
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @   5770339 ps: (kmac_csr_assert_fpv.sv:515) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @   5770339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test kmac_tl_intg_err has 4 failures.

4.kmac_tl_intg_err.99105713391220175698092653516720459487290794386430061696377598498570951395524
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
  UVM_ERROR @  35886435 ps: (kmac_csr_assert_fpv.sv:545) [ASSERT FAILED] prefix_10_rd_A
  UVM_INFO @  35886435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_tl_intg_err.104718197705149454296181018836701050753540509418479102631761261796221921766053
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  37266895 ps: (kmac_csr_assert_fpv.sv:520) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  37266895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 2.kmac_stress_all_with_rand_reset.45773319340180879748527523448831708120977936914919657851405569350227624993039
    Line 137, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1925146508 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1925146508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.kmac_stress_all_with_rand_reset.59972054258709540453506916238193658929073134613079005810056016132540269541694
    Line 91, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 148522470 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 148522470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

Test kmac_stress_all has 2 failures.

18.kmac_stress_all.70000139575712849122597032869682411265832011159854803590068915598266372946359
Line 146, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/18.kmac_stress_all/latest/run.log

  UVM_ERROR @ 60773783846 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 60773783846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.kmac_stress_all.47260046511282542788186426054536749080249377658531120091352554020193794136285
Line 378, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/46.kmac_stress_all/latest/run.log

  UVM_ERROR @ 88034766062 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 88034766062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 3.kmac_shadow_reg_errors_with_csr_rw.28464096413192143066938020620176550859816616310134816138025643684147913605319
    Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  11777900 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (892038843 [0x352b6ebb] vs 2137384713 [0x7f65e709]) Regname: kmac_reg_block.prefix_2.prefix_0 reset value: 0x0
  UVM_INFO @  11777900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```