KMAC/UNMASKED Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: `f19c6a3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.035m	3.821ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.420s	14.424us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.570s	71.302us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.640s	1.897ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.370s	4.108ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.870s	78.755us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.570s	71.302us	20	20	100.00
		kmac_csr_aliasing	9.370s	4.108ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.190s	10.117us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.910s	36.370us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.987m	132.141ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.660m	140.198ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.316m	253.820ms	5	5	100.00
		kmac_test_vectors_sha3_256	30.581m	90.872ms	5	5	100.00
		kmac_test_vectors_sha3_384	23.099m	91.466ms	5	5	100.00
		kmac_test_vectors_sha3_512	22.390m	931.618ms	5	5	100.00
		kmac_test_vectors_shake_128	39.600m	253.150ms	5	5	100.00
		kmac_test_vectors_shake_256	30.226m	171.330ms	5	5	100.00
		kmac_test_vectors_kmac	3.650s	110.484us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.690s	601.216us	5	5	100.00
V2	sideload	kmac_sideload	6.719m	73.831ms	50	50	100.00
V2	app	kmac_app	7.004m	239.348ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.013m	17.214ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.267m	24.991ms	50	50	100.00
V2	error	kmac_error	6.699m	86.560ms	50	50	100.00
V2	key_error	kmac_key_error	20.370s	26.693ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.183m	10.069ms	35	50	70.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.600s	1.517ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.850s	1.916ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.177m	33.747ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	27.340s	2.586ms	50	50	100.00
V2	stress_all	kmac_stress_all	43.471m	888.899ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.320s	27.473us	50	50	100.00
V2	alert_test	kmac_alert_test	2.330s	37.831us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.390s	418.718us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.390s	418.718us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.420s	14.424us	5	5	100.00
		kmac_csr_rw	2.570s	71.302us	20	20	100.00
		kmac_csr_aliasing	9.370s	4.108ms	5	5	100.00
		kmac_same_csr_outstanding	4.420s	136.218us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.420s	14.424us	5	5	100.00
		kmac_csr_rw	2.570s	71.302us	20	20	100.00
		kmac_csr_aliasing	9.370s	4.108ms	5	5	100.00
		kmac_same_csr_outstanding	4.420s	136.218us	20	20	100.00
V2		TOTAL			725	740	97.97
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.300s	433.735us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.300s	433.735us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.300s	433.735us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.300s	433.735us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.170s	782.179us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	44.600s	6.570ms	5	5	100.00
		kmac_tl_intg_err	5.970s	232.689us	15	20	75.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.970s	232.689us	15	20	75.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	27.340s	2.586ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.035m	3.821ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.719m	73.831ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.300s	433.735us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	44.600s	6.570ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	44.600s	6.570ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	44.600s	6.570ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.035m	3.821ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	27.340s	2.586ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	44.600s	6.570ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.864m	15.513ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.035m	3.821ms	50	50	100.00
V2S		TOTAL			67	75	89.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.907m	5.487ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			910	940	96.81

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.68	97.08	94.46	100.00	72.73	95.90	99.35	96.27

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 8 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

0.kmac_shadow_reg_errors_with_csr_rw.100230418748613616824373193944320182020094298615915485559877126096396720025084
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  53394361 ps: (kmac_csr_assert_fpv.sv:500) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  53394361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_shadow_reg_errors_with_csr_rw.13454029854826467982654937842954694880529417486485078351120072690416337316805
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  45093093 ps: (kmac_csr_assert_fpv.sv:540) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  45093093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_tl_intg_err has 5 failures.

2.kmac_tl_intg_err.7683732403578777815290026591331100065665282742943337873774762695009379739800
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  39145684 ps: (kmac_csr_assert_fpv.sv:535) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  39145684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_tl_intg_err.94545758119363509961310894554252968164746542336938738543686730601085183028223
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  43905142 ps: (kmac_csr_assert_fpv.sv:490) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  43905142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.54818368335105417663872226220742709939736007454569810694712146493607316014197
    Line 114, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 867321885 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 867321885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.31778698661695852013658169299150359989102097023031384476310399428251177172211
    Line 140, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2283374156 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2283374156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 3.kmac_sideload_invalid.10909455692656698593768941763977779827386561009974758238978113528611630856026
    Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10052572005 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf2472000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10052572005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 20.kmac_sideload_invalid.18759627334166124737605510734518980690601069874788649566883763799282106406420
    Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10294115758 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7e24d000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10294115758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 13.kmac_sideload_invalid.81603914962102321929867062206680260738726947977808096296225035916028227875416
    Line 89, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/13.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10549883877 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcb4df000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
  UVM_INFO @ 10549883877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 43.kmac_sideload_invalid.50778651318909634319777589130394726615050175396144556271864063440663886385888
    Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10313113146 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x74189000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
  UVM_INFO @ 10313113146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 18.kmac_sideload_invalid.16588132767860482866608376912297716642033372198551823488639861304331582577696
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10107564431 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6d585000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10107564431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 39.kmac_sideload_invalid.94027124574771949298206983187241930822935292935774206685953184245219756272959
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/39.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10009708965 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc4b64000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10009708965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 29.kmac_sideload_invalid.21900813703003138478515256676027367471154524468891245463222806897839601321261
    Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10068709347 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x33286000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10068709347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 42.kmac_sideload_invalid.9750344139305920779482411826053924190721657733317894650291080627106263729992
    Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10076537617 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x26bc2000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10076537617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 32.kmac_sideload_invalid.57461426346350502158519292072415983270233492551930539566577996215288430114880
    Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10037782813 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb40ee000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10037782813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 44.kmac_sideload_invalid.103699377704652614349598686912345097491531091169650232085245275629084496032562
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10019878274 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x593e6000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10019878274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 2.kmac_sideload_invalid.58703001554961550236266880408110565462401269173252753472835870910093273133856
    Line 97, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10545671795 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x51006000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
  UVM_INFO @ 10545671795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 21.kmac_sideload_invalid.23049245508573846272526452213939819822242750665233184262518953205142581331925
    Line 99, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10406482656 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x99df8000, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
  UVM_INFO @ 10406482656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 30.kmac_sideload_invalid.66341278537856369975263221760114527285411896471794357091754596300697409113569
    Line 89, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/30.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10125023063 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x88935000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
  UVM_INFO @ 10125023063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 38.kmac_sideload_invalid.14619583829227463504930038179139959662448616893807093289122353061911175645517
    Line 98, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 11286752210 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9da39000, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
  UVM_INFO @ 11286752210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 49.kmac_sideload_invalid.32042426950689536042609140684406656464733692276256157747872524590072412912039
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/49.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10176262735 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf8720000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10176262735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```