OTBN Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: `f19c6a3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	1.017m	98.224us	1	1	100.00
V1	single_binary	otbn_single	1.767m	437.801us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	17.625us	5	5	100.00
V1	csr_rw	otbn_csr_rw	8.000s	21.373us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	27.193us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	9.000s	22.295us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	33.308us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	8.000s	21.373us	20	20	100.00
		otbn_csr_aliasing	9.000s	22.295us	5	5	100.00
V1	mem_walk	otbn_mem_walk	28.000s	361.054us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	17.000s	396.461us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.033m	122.265us	10	10	100.00
V2	multi_error	otbn_multi_err	1.433m	173.661us	1	1	100.00
V2	back_to_back	otbn_multi	6.500m	14.312ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.033m	333.589us	10	10	100.00
V2	lc_escalation	otbn_escalate	1.700m	406.387us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	12.000s	57.770us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	42.000s	464.827us	10	10	100.00
V2	alert_test	otbn_alert_test	13.000s	28.534us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	16.268us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	103.934us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	103.934us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	17.625us	5	5	100.00
		otbn_csr_rw	8.000s	21.373us	20	20	100.00
		otbn_csr_aliasing	9.000s	22.295us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	23.715us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	17.625us	5	5	100.00
		otbn_csr_rw	8.000s	21.373us	20	20	100.00
		otbn_csr_aliasing	9.000s	22.295us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	23.715us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	49.000s	31.282us	10	10	100.00
		otbn_dmem_err	49.000s	23.545us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	54.000s	79.702us	5	5	100.00
		otbn_controller_ispr_rdata_err	29.000s	77.483us	5	5	100.00
		otbn_mac_bignum_acc_err	1.183m	265.710us	5	5	100.00
		otbn_urnd_err	11.000s	46.304us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	20.469us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	44.625us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	37.827us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	4.333m	1.076ms	2	5	40.00
		otbn_tl_intg_err	54.000s	267.916us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	31.000s	718.207us	18	20	90.00
V2S	prim_fsm_check	otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	1.017m	98.224us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	49.000s	23.545us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	49.000s	31.282us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	54.000s	267.916us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.700m	406.387us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	49.000s	31.282us	10	10	100.00
		otbn_dmem_err	49.000s	23.545us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	57.770us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	20.469us	5	5	100.00
		otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.767m	437.801us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	49.000s	31.282us	10	10	100.00
		otbn_dmem_err	49.000s	23.545us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	57.770us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	20.469us	5	5	100.00
		otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.700m	406.387us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	49.000s	31.282us	10	10	100.00
		otbn_dmem_err	49.000s	23.545us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	57.770us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	20.469us	5	5	100.00
		otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.767m	437.801us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	72.925us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	17.000s	35.687us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	36.000s	224.529us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	36.000s	224.529us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	42.000s	142.816us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	22.000s	41.632us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	30.166us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	30.166us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	19.310us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.767m	437.801us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.767m	437.801us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.767m	437.801us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	6.500m	14.312ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.767m	437.801us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.767m	437.801us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	18.000s	74.183us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.767m	437.801us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.333m	1.076ms	2	5	40.00
V2S		TOTAL			157	163	96.32
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	8.850m	2.137ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			573	585	97.95

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.06	99.61	95.56	99.72	93.27	93.13	100.00	97.50	99.57

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.45589247498419775206720753712529792965678901447043944647524733261186187215513
Line 131, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 42567727 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 42567727 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  42567727 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  42567727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_cm.41249752596482023560344438762667517096338355855495746039515909344661788560609
Line 100, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 86352315 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 86352315 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  86352315 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  86352315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 2.otbn_stress_all_with_rand_reset.4731643281242285257165310354434356194936945617804128096863652529546269364304
    Line 327, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 404278055 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 404278055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.otbn_stress_all_with_rand_reset.91505572423843547892736019961888125929339627154996666184676104300192896563265
    Line 182, in log /nightly/runs/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 277195516 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 277195516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:

Test otbn_passthru_mem_tl_intg_err has 2 failures.

0.otbn_passthru_mem_tl_intg_err.70609679996510649762823897298145890356120780901651737465306656023069884140129
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @   3073693 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @   3073693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_passthru_mem_tl_intg_err.100890665448104872679750404127044635830299951348834411185556195126704231056958
Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @  25046536 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  25046536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.8915656283669208916787716669646337201564993999170088112758091472011405466691
    Line 491, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2087955230 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2087955230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed has 1 failures:

Test otbn_partial_wipe has 1 failures.

3.otbn_partial_wipe.7161882667327640527120378574217901191749263062142374223996627849336655613038
Line 103, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 7618404 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
  UVM_ERROR @   7618404 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
  UVM_INFO @   7618404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:701) virtual_sequencer [otbn_imem_err_vseq] expect alert:fatal to fire has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.26707417510087820256777043801306084678273441844063802182662597051851369083445
    Line 173, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 786415712 ps: (cip_base_vseq.sv:701) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] expect alert:fatal to fire
  UVM_INFO @ 786415712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 28.otbn_escalate.53484096254414805903281318225900436206943095028244164414753621452774643281350
    Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/28.otbn_escalate/latest/run.log
```
  UVM_ERROR @   7179882 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   7179882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```