ROM_CTRL/32KB Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: f19c6a3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.780s	249.029us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.400s	237.785us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	9.570s	1.074ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.150s	137.983us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.980s	133.596us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.430s	185.883us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	9.570s	1.074ms	20	20	100.00
		rom_ctrl_csr_aliasing	6.980s	133.596us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	8.240s	4.503ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.230s	127.995us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.770s	188.420us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	24.400s	1.975ms	19	20	95.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	13.620s	300.889us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	7.730s	171.017us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.110s	173.295us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.110s	173.295us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.400s	237.785us	5	5	100.00
		rom_ctrl_csr_rw	9.570s	1.074ms	20	20	100.00
		rom_ctrl_csr_aliasing	6.980s	133.596us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.170s	2.011ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.400s	237.785us	5	5	100.00
		rom_ctrl_csr_rw	9.570s	1.074ms	20	20	100.00
		rom_ctrl_csr_aliasing	6.980s	133.596us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.170s	2.011ms	20	20	100.00
V2		TOTAL			113	114	99.12
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.699m	8.469ms	14	20	70.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	27.760s	1.123ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.768m	2.137ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.060m	867.862us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.768m	2.137ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.768m	2.137ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.699m	8.469ms	14	20	70.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.699m	8.469ms	14	20	70.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.699m	8.469ms	14	20	70.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.699m	8.469ms	14	20	70.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.699m	8.469ms	14	20	70.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.768m	2.137ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.768m	2.137ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.780s	249.029us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.780s	249.029us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.780s	249.029us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.060m	867.862us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.699m	8.469ms	14	20	70.00
		rom_ctrl_kmac_err_chk	13.620s	300.889us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.699m	8.469ms	14	20	70.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.699m	8.469ms	14	20	70.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.699m	8.469ms	14	20	70.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	27.760s	1.123ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.768m	2.137ms	5	5	100.00
V2S		TOTAL			59	65	90.77
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	10.799m	6.269ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			259	266	97.37

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	100.00	99.41	100.00	100.00	100.00	98.97	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 5 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 5 failures.

    • 5.rom_ctrl_corrupt_sig_fatal_chk.105339964412159678411997547167753017361193863423296402090017426884621876674587
      Line 92, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 2836591282 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 2836591282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 12.rom_ctrl_corrupt_sig_fatal_chk.57941731022975209752894838058509978028768180671370853179044035795836981260155
      Line 106, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1659705377 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1659705377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• Offending '(counter_lnt -> kmac_rom_vld_o)' has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 11.rom_ctrl_corrupt_sig_fatal_chk.88550541728379615916113853115331069012253672487697135749277056486297195397560
      Line 106, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

            Offending '(counter_lnt -> kmac_rom_vld_o)'
        UVM_ERROR @ 6320405341 ps: (rom_ctrl_fsm.sv:317) [ASSERT FAILED] CounterLntImpliesKmacRomVldO_A
        UVM_INFO @ 6320405341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:695) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire has 1 failures:

  • Test rom_ctrl_stress_all has 1 failures.

    • 12.rom_ctrl_stress_all.42370201698111606871309311379779032642320782383646417269994138722646563671131
      Line 80, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 1112157112 ps: (cip_base_vseq.sv:695) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 1112157112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---