RV_TIMER Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: f19c6a3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.050s	56.820us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.980s	53.552us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.240s	25.810us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.870s	1.402ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.350s	14.125us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.330s	20.973us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.240s	25.810us	20	20	100.00
		rv_timer_csr_aliasing	2.350s	14.125us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	3.720s	1.387ms	20	20	100.00
V2	disabled	rv_timer_disabled	3.310s	1.306ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	13.642m	5.182s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	13.642m	5.182s	10	10	100.00
V2	stress	rv_timer_stress_all	8.360s	4.359ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.150s	24.783us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.180s	21.683us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.790s	631.993us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.790s	631.993us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.980s	53.552us	5	5	100.00
		rv_timer_csr_rw	2.240s	25.810us	20	20	100.00
		rv_timer_csr_aliasing	2.350s	14.125us	5	5	100.00
		rv_timer_same_csr_outstanding	2.110s	116.082us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.980s	53.552us	5	5	100.00
		rv_timer_csr_rw	2.240s	25.810us	20	20	100.00
		rv_timer_csr_aliasing	2.350s	14.125us	5	5	100.00
		rv_timer_same_csr_outstanding	2.110s	116.082us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.190s	476.546us	5	5	100.00
		rv_timer_tl_intg_err	2.720s	165.659us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.720s	165.659us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	49.270s	91.918ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	1.990s	13.105us	10	10	100.00
		rv_timer_max	1.890s	24.740us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00