SPI_DEVICE/1R1W Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: `f19c6a3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.436m	138.570ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.780s	38.389us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.820s	192.098us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.390s	38.574ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.710s	1.185ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.550s	135.079us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.820s	192.098us	20	20	100.00
		spi_device_csr_aliasing	19.710s	1.185ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.230s	45.950us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.630s	83.470us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.390s	19.781us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.290s	2.552us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	2.160s	8.921us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	9.700s	506.076us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.700s	506.076us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	35.670s	16.745ms	50	50	100.00
		spi_device_tpm_sts_read	2.560s	243.632us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	37.260s	7.407ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	26.930s	20.174ms	50	50	100.00
		spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	33.800s	31.016ms	50	50	100.00
		spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	33.800s	31.016ms	50	50	100.00
		spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	36.180s	20.220ms	50	50	100.00
		spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	36.180s	20.220ms	50	50	100.00
		spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	36.180s	20.220ms	50	50	100.00
		spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	36.180s	20.220ms	50	50	100.00
		spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	36.180s	20.220ms	50	50	100.00
		spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	40.090s	66.163ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.760m	17.287ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.760m	17.287ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.760m	17.287ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	58.870s	5.519ms	50	50	100.00
		spi_device_read_buffer_direct	23.320s	2.272ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.760m	17.287ms	50	50	100.00
		spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.939m	108.999ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	15.840s	1.650ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	15.840s	1.650ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.436m	138.570ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.682m	125.727ms	50	50	100.00
V2	stress_all	spi_device_stress_all	9.378m	351.641ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.340s	31.091us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.410s	23.146us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.150s	90.004us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.150s	90.004us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.780s	38.389us	5	5	100.00
		spi_device_csr_rw	3.820s	192.098us	20	20	100.00
		spi_device_csr_aliasing	19.710s	1.185ms	5	5	100.00
		spi_device_same_csr_outstanding	5.730s	152.721us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.780s	38.389us	5	5	100.00
		spi_device_csr_rw	3.820s	192.098us	20	20	100.00
		spi_device_csr_aliasing	19.710s	1.185ms	5	5	100.00
		spi_device_same_csr_outstanding	5.730s	152.721us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.650s	211.512us	5	5	100.00
		spi_device_tl_intg_err	21.270s	1.069ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.270s	1.069ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.045m	164.651ms	49	50	98.00
		TOTAL			1129	1151	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.53	98.98	96.55	83.54	89.36	98.39	95.66	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.46916345272909628779311452083254220125983974757970709150180781807914471975886
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2089569 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[49])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2089569 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2089569 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[945])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.18591622587220330050703224554572922577276717824051852069659070883841053710911
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1160777 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[71])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1160777 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1160777 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[967])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.21419290580419567091444085142346123612729605022335966353966069016919935021122
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   6389451 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5577a7 [10101010111011110100111] vs 0x0 [0])
  UVM_ERROR @   6390451 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x455c66 [10001010101110001100110] vs 0x0 [0])
  UVM_ERROR @   6482451 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x14d3a2 [101001101001110100010] vs 0x0 [0])
  UVM_ERROR @   6512451 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x931805 [100100110001100000000101] vs 0x0 [0])
  UVM_ERROR @   6528451 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8f4a28 [100011110100101000101000] vs 0x0 [0])

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 34.spi_device_flash_mode_ignore_cmds.13463999232899643698040017345163144684152901038266486116266102456763710490331
    Log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```