SPI_HOST Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: f19c6a3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.650m	7.743ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	18.705us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	16.218us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	729.979us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	112.908us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	6.000s	179.355us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	16.218us	20	20	100.00
		spi_host_csr_aliasing	4.000s	112.908us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	14.723us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	36.645us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	37.000s	23.382us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	42.000s	1.659ms	50	50	100.00
		spi_host_error_cmd	37.000s	38.106us	50	50	100.00
		spi_host_event	3.300m	6.853ms	50	50	100.00
V2	clock_rate	spi_host_speed	39.000s	370.007us	50	50	100.00
V2	speed	spi_host_speed	39.000s	370.007us	50	50	100.00
V2	chip_select_timing	spi_host_speed	39.000s	370.007us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	3.450m	11.330ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	36.000s	37.643us	50	50	100.00
V2	cpol_cpha	spi_host_speed	39.000s	370.007us	50	50	100.00
V2	full_cycle	spi_host_speed	39.000s	370.007us	50	50	100.00
V2	duplex	spi_host_smoke	1.650m	7.743ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.650m	7.743ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.950m	5.681ms	50	50	100.00
V2	spien	spi_host_spien	1.350m	5.210ms	50	50	100.00
V2	stall	spi_host_status_stall	12.433m	21.764ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	40.000s	7.667ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	42.000s	1.659ms	50	50	100.00
V2	alert_test	spi_host_alert_test	33.000s	18.705us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	41.503us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	164.146us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	164.146us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	18.705us	5	5	100.00
		spi_host_csr_rw	5.000s	16.218us	20	20	100.00
		spi_host_csr_aliasing	4.000s	112.908us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	132.860us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	18.705us	5	5	100.00
		spi_host_csr_rw	5.000s	16.218us	20	20	100.00
		spi_host_csr_aliasing	4.000s	112.908us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	132.860us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	97.646us	20	20	100.00
		spi_host_sec_cm	33.000s	82.206us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	97.646us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	10.283m	83.393ms	10	10	100.00
		TOTAL			838	840	99.76

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.25	96.78	93.27	98.69	94.36	88.02	100.00	97.27	90.00

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 2 failures:
  • Test spi_host_status_stall has 2 failures.

    • 18.spi_host_status_stall.62597930845675797846745860541526921433840407484965947780924693104905826454237
      Line 835, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/18.spi_host_status_stall/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 619230304 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
        UVM_ERROR @ 619230304 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=619230000 ps
        UVM_INFO @ 619230304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 44.spi_host_status_stall.2461086175436877839764742377320418140438897416371812283267550244445262957959
      Line 1580, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 9122446896 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
        UVM_ERROR @ 9122446896 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=9122447000 ps
        UVM_INFO @ 9122446896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---