SRAM_CTRL/MAIN Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: f19c6a3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.581m	3.226ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.140s	28.485us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.160s	13.298us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.390s	119.006us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.180s	17.989us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.420s	706.483us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.160s	13.298us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	17.989us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.589m	34.441ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.856m	5.796ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	19.704m	18.104ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.712m	24.241ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	36.253m	163.589ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.576m	206.043ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.684m	129.932ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.145m	86.219ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.706m	2.163ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.639m	26.740ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.647m	823.342us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.630m	799.020us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.585m	5.705ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	15.997m	34.716ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.000s	3.045ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.760h	651.144ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.170s	12.004us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.260s	154.783us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.260s	154.783us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.140s	28.485us	5	5	100.00
		sram_ctrl_csr_rw	2.160s	13.298us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	17.989us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.270s	60.988us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.140s	28.485us	5	5	100.00
		sram_ctrl_csr_rw	2.160s	13.298us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	17.989us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.270s	60.988us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	51.200s	70.323ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.020s	9.904us	0	5	0.00
		sram_ctrl_tl_intg_err	5.680s	3.280ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.020s	9.904us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.680s	3.280ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	15.997m	34.716ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	15.997m	34.716ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.160s	13.298us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.145m	86.219ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.145m	86.219ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.145m	86.219ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.684m	129.932ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.660s	7.446ms	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	51.200s	70.323ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.900s	4.740ms	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.581m	3.226ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.581m	3.226ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.145m	86.219ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.020s	9.904us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.684m	129.932ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.020s	9.904us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.020s	9.904us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.581m	3.226ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.020s	9.904us	0	5	0.00
V2S		TOTAL			125	145	86.21
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.236m	4.452ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1170	1190	98.32

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	99.29	93.01	85.18	100.00	98.03	98.59	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 10 failures:
  • Test sram_ctrl_readback_err has 10 failures.

    • 5.sram_ctrl_readback_err.47604875979055607785955310494170532389041191615024292926695071875364448208206
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1324656984 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x2d) != exp (0x5)
        UVM_INFO @ 1324656984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.sram_ctrl_readback_err.30254002777779807975099177550118988546500202139541787407415169180851854580294
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1341619416 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x71) != exp (0x17)
        UVM_INFO @ 1341619416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:
  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 9.sram_ctrl_mubi_enc_err.84569626299231829031282287030718694192122225747517741428832536068017652994395
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1375638693 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1375638693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 12.sram_ctrl_mubi_enc_err.36114414932469337471768260542883776872351221837121142733369602218069220419824
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 876583382 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 876583382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 1.sram_ctrl_sec_cm.18839080249920708890362971262203048551792721703459969616598694867599000034549
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  12835297 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  12835297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.47475399686946765861936614046307683302097653809601660055820629288220928870110
      Line 104, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9904452 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9904452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.49337337221278856969832277620627050866010367915362749561729050299392854903525
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   1054265 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   1054265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---