SRAM_CTRL/RET Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: f19c6a3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.685m	3.269ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.180s	33.707us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.030s	35.602us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.370s	693.812us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.180s	53.712us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	26.660s	10.001ms	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.030s	35.602us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	53.712us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	17.550s	6.275ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.910s	627.253us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	25.421m	21.902ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.427m	8.607ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.506m	4.493ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.792m	3.520ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	14.780s	1.115ms	50	50	100.00
V2	executable	sram_ctrl_executable	18.857m	3.432ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.474m	660.875us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.726m	30.424ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.611m	194.492us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.525m	473.453us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.730m	1.650ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.691m	15.862ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.320s	31.635us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.312h	300.960ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.110s	37.225us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.530s	808.648us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.530s	808.648us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.180s	33.707us	5	5	100.00
		sram_ctrl_csr_rw	2.030s	35.602us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	53.712us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.160s	52.463us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.180s	33.707us	5	5	100.00
		sram_ctrl_csr_rw	2.030s	35.602us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	53.712us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.160s	52.463us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.180s	740.799us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.270s	6.209us	0	5	0.00
		sram_ctrl_tl_intg_err	3.920s	280.778us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.270s	6.209us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.920s	280.778us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.691m	15.862ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.691m	15.862ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.030s	35.602us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	18.857m	3.432ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	18.857m	3.432ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	18.857m	3.432ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	14.780s	1.115ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.620s	79.166us	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.180s	740.799us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.700s	372.703us	34	50	68.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.685m	3.269ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.685m	3.269ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	18.857m	3.432ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.270s	6.209us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	14.780s	1.115ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.270s	6.209us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.270s	6.209us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.685m	3.269ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.270s	6.209us	0	5	0.00
V2S		TOTAL			118	145	81.38
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.296m	2.603ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1160	1190	97.48

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.26	93.01	85.10	100.00	97.99	98.58	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 16 failures:

  • Test sram_ctrl_readback_err has 16 failures.

    • 0.sram_ctrl_readback_err.57387055734261837950550642962475452733646257901973045545174493003338546449912
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  23508653 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x45) != exp (0x4)
        UVM_INFO @  23508653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_readback_err.42766633624787748414497256017036654530821517694542892854298579122934147412252
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  92938818 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x68) != exp (0x1d)
        UVM_INFO @  92938818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 14 more failures.

• Offending 'reqfifo_rvalid' has 6 failures:

  • Test sram_ctrl_mubi_enc_err has 6 failures.

    • 6.sram_ctrl_mubi_enc_err.73501459023306463518676620376427244859146418733933731522959876257552845860469
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  26356074 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  26356074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_mubi_enc_err.71978982132111700864562358638095587293802289100368703948624147330691629261901
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  92100766 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  92100766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:

  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.3491650409596544539930210377761350158971050777266197806953104001980334641573
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2466575 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2466575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.55421982269925744895415490880142747934501105659908308906781932638536381408651
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2930864 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2930864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 2.sram_ctrl_csr_mem_rw_with_rand_reset.112081125818566266613659421543512382554764531115601236853733062366379464056127
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  33657380 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  33657380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.15273640606182933375003997086285886864065256309206057459719037741889997398275
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   5266628 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   5266628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 8.sram_ctrl_csr_mem_rw_with_rand_reset.18023013486404446528347369692881827642140795902679083368206453650749723634289
      Line 91, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_FATAL @ 10001104261 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
        UVM_INFO @ 10001104261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 16.sram_ctrl_csr_mem_rw_with_rand_reset.93068144056889040641727321346822574914047806813776928679503473913681966423282
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 119871743 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (10 [0xa] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
        UVM_INFO @ 119871743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---