UART Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: f19c6a3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	26.920s	5.910ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.960s	18.257us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.050s	61.420us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.360s	116.207us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.960s	65.315us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.310s	37.908us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.050s	61.420us	20	20	100.00
		uart_csr_aliasing	1.960s	65.315us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.387m	111.468ms	50	50	100.00
V2	parity	uart_smoke	26.920s	5.910ms	50	50	100.00
		uart_tx_rx	3.387m	111.468ms	50	50	100.00
V2	parity_error	uart_intr	13.999m	526.474ms	49	50	98.00
		uart_rx_parity_err	4.827m	194.552ms	50	50	100.00
V2	watermark	uart_tx_rx	3.387m	111.468ms	50	50	100.00
		uart_intr	13.999m	526.474ms	49	50	98.00
V2	fifo_full	uart_fifo_full	13.558m	278.256ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.964m	162.940ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	13.763m	232.344ms	300	300	100.00
V2	rx_frame_err	uart_intr	13.999m	526.474ms	49	50	98.00
V2	rx_break_err	uart_intr	13.999m	526.474ms	49	50	98.00
V2	rx_timeout	uart_intr	13.999m	526.474ms	49	50	98.00
V2	perf	uart_perf	13.885m	22.539ms	50	50	100.00
V2	sys_loopback	uart_loopback	36.570s	10.186ms	50	50	100.00
V2	line_loopback	uart_loopback	36.570s	10.186ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.831m	167.347ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.151m	69.217ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	52.620s	12.142ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.047m	7.321ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	16.550m	121.060ms	50	50	100.00
V2	stress_all	uart_stress_all	18.680m	510.083ms	50	50	100.00
V2	alert_test	uart_alert_test	2.200s	11.110us	50	50	100.00
V2	intr_test	uart_intr_test	1.970s	27.136us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.850s	40.388us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.850s	40.388us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.960s	18.257us	5	5	100.00
		uart_csr_rw	2.050s	61.420us	20	20	100.00
		uart_csr_aliasing	1.960s	65.315us	5	5	100.00
		uart_same_csr_outstanding	2.140s	123.930us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.960s	18.257us	5	5	100.00
		uart_csr_rw	2.050s	61.420us	20	20	100.00
		uart_csr_aliasing	1.960s	65.315us	5	5	100.00
		uart_same_csr_outstanding	2.140s	123.930us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	2.640s	66.953us	5	5	100.00
		uart_tl_intg_err	2.780s	476.193us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.780s	476.193us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.339m	6.489ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1316	1320	99.70

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.17	98.25	91.55	--	98.14	100.00	99.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:832) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test uart_stress_all_with_rand_reset has 2 failures.

    • 21.uart_stress_all_with_rand_reset.111207597042460765322701170421831131868439389042611868039714840830256979748354
      Line 81, in log /nightly/runs/scratch/master/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 759214651 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 759214651 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 759255887 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 1/5
      

    • 61.uart_stress_all_with_rand_reset.24511931663662926431845066630713184367731399670125934595654683631385738020719
      Line 125, in log /nightly/runs/scratch/master/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1191846680 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1191846680 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 6/10
        UVM_INFO @ 1191896680 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 6/10
      

• UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxDone has 1 failures:

  • Test uart_intr has 1 failures.

    • 13.uart_intr.23089016441480887900902003267955601103553220016589683541359990143678890804530
      Line 121, in log /nightly/runs/scratch/master/uart-sim-vcs/13.uart_intr/latest/run.log

        UVM_ERROR @ 68825740655 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxDone
        UVM_INFO @ 68834340655 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
        Testing TxDone
        UVM_INFO @ 69458140655 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
        Testing RxWatermark
      

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 47.uart_noise_filter.255020163702472793152330005486970311903238070535514893910583023648138385087
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/47.uart_noise_filter/latest/run.log

        UVM_ERROR @   4151367 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 6886463655 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/12
        UVM_INFO @ 7160400239 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/12
        UVM_INFO @ 16322735103 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/12
        UVM_INFO @ 18643430823 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/12