CHIP Simulation Results

Friday May 16 2025 17:35:20 UTC

GitHub Revision: `f19c6a3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.174m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.174m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.338m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.276m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	47.514s		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.201m	5.326ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.201m	5.326ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.201m	5.326ms	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	51.950s	10.120us	0	3	0.00
		chip_sw_example_manufacturer	3.016m		0	3	0.00
		chip_sw_example_concurrency	6.263m	4.730ms	3	3	100.00
		chip_sw_uart_smoketest_signed	23.537s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	17.460s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	17.970s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	17.970s		0	3	0.00
V1	xbar_smoke	xbar_smoke	35.000s	67.951us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.925m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	16.378m	10.866ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	7.560m	3.793ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	24.817s		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	17.345s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	30.613s		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	41.083s		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.930s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.930s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.504m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.199m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.698m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.698m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	5.160m	4.552ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.614m	3.167ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.331m	15.229ms	0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	18.450s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	17.112s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	21.224m	27.123ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	7.424m	4.870ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	36.242m	18.018ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	36.242m	18.018ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	18.532s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.567m	6.033ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.567m	6.033ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.654m	18.017ms	0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	6.349m	4.408ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.600m	5.596ms	3	3	100.00
		chip_sw_aes_idle	5.456m	4.804ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.300m	3.758ms	3	3	100.00
		chip_sw_kmac_idle	6.880m	4.977ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	19.794m	12.017ms	0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	19.196m	12.015ms	0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	20.904m	12.015ms	0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	21.680m	12.015ms	0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	17.747s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.211s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	22.065s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.378s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.609s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.026s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.461s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	17.747s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.211s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	22.065s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.378s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.609s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.026s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.461s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.612s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.013m	10.360us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.006m	10.300us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.069m	10.160us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.225m	10.120us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.239s		0	3	0.00
		chip_sw_clkmgr_jitter	4.779m	4.189ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.551m	5.215ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	23.223s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.287m	10.220us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.334m	10.180us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1.435m	10.280us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.314m	10.280us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.353m	10.300us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	20.963s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	18.440s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	16.516s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	20.617s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	34.699m	17.034ms	92	100	92.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	12.873m	11.635ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	7.567m	6.033ms	0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	28.488s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	12.873m	11.635ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	25.284s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	27.017s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	16.263s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	18.430s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	24.265s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	34.699m	17.034ms	92	100	92.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.331m	15.229ms	0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	36.007m	20.024ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.425m	9.743ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.570m	9.258ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.715m	4.953ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	34.699m	17.034ms	92	100	92.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	18.084s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	18.165s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	34.699m	17.034ms	92	100	92.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	18.093s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.570m	9.258ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	17.876s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	21.401s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	18.041s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.850s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.829s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	18.434s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	18.165s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	28.918s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.611s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	28.918s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	28.918s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	28.918s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	9.280m	10.004ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	22.133s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	22.518s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	20.738s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	34.585s		0	3	0.00
		chip_sw_lc_ctrl_transition	28.918s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	10.944m	8.309ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	13.438m	11.335ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	22.805s		0	3	0.00
		chip_prim_tl_access	24.988m	26.626ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	17.747s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.211s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	22.065s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.378s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.609s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.026s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.461s		0	3	0.00
		chip_rv_dm_lc_disabled	21.224m	27.123ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.999m	5.396ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	1.013m	10.360us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.869m	4.156ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.456m	4.804ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.258m	5.081ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	1.006m	10.300us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.300m	3.758ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.971m	5.684ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.905m	5.510ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.225m	10.120us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	10.944m	8.309ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	28.918s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.020m	10.240us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	7.537m	4.607ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	6.880m	4.977ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	18.096s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	18.096s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	19.991s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.338m	5.063ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	18.526s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	10.944m	8.309ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.069m	10.160us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	18.853s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	18.612s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.600m	5.596ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.600m	5.596ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.600m	5.596ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	10.752m	6.975ms	2	3	66.67
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	13.438m	11.335ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	13.438m	11.335ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	13.598m	10.426ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.239s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	22.805s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	34.699m	17.034ms	92	100	92.00
		chip_sw_data_integrity_escalation	2.698m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	28.918s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	10.752m	6.975ms	2	3	66.67
		chip_sw_keymgr_dpe_key_derivation	10.944m	8.309ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	13.598m	10.426ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.761m	4.807ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	10.752m	6.975ms	2	3	66.67
		chip_sw_keymgr_dpe_key_derivation	10.944m	8.309ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	13.598m	10.426ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.761m	4.807ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	28.918s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.020s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.611s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	22.133s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	22.518s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	20.738s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	34.585s		0	3	0.00
		chip_sw_lc_ctrl_transition	28.918s		0	15	0.00
		chip_prim_tl_access	24.988m	26.626ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	24.988m	26.626ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	17.978s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	28.845s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	18.440s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.612s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.013m	10.360us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.006m	10.300us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.069m	10.160us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.225m	10.120us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.239s		0	3	0.00
		chip_sw_clkmgr_jitter	4.779m	4.189ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	10.377m	6.110ms	3	3	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	10.377m	6.110ms	3	3	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	6.247m	4.592ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	5.103m	5.101ms	0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	6.475m	4.958ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	10.961m	5.198ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.862m	4.471ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.625m	6.030ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	6.761m	4.807ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	36.007m	20.024ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	36.007m	20.024ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	5.951m	4.581ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.724m	4.980ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.413m	4.503ms	3	3	100.00
		chip_sw_csrng_smoketest	6.234m	5.478ms	3	3	100.00
		chip_sw_gpio_smoketest	5.424m	5.857ms	3	3	100.00
		chip_sw_hmac_smoketest	6.930m	4.469ms	3	3	100.00
		chip_sw_kmac_smoketest	7.812m	5.727ms	3	3	100.00
		chip_sw_otbn_smoketest	8.156m	4.715ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	4.978m	4.798ms	3	3	100.00
		chip_sw_rv_plic_smoketest	6.140m	4.837ms	3	3	100.00
		chip_sw_rv_timer_smoketest	6.950m	5.943ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.741m	5.673ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	6.345m	5.682ms	3	3	100.00
		chip_sw_uart_smoketest	5.747m	5.097ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	33.086s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	23.537s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.925m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	18.449s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.919m	4.919ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	5.648m	5.471ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	5.306m	5.850ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	6.518m	5.876ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	16.123s		0	3	0.00
		chip_rv_dm_lc_disabled	21.224m	27.123ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	22.864s		0	3	0.00
		chip_sw_lc_walkthrough_prod	18.864s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	17.384s		0	3	0.00
		chip_sw_lc_walkthrough_rma	26.813s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	16.123s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	22.013s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	40.216s		0	3	0.00
		rom_volatile_raw_unlock	17.777s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	17.767s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.656m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.661m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	5.084m	3.372ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	5.084m	3.372ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	17.970s		0	3	0.00
		chip_same_csr_outstanding	18.250s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	17.970s		0	3	0.00
		chip_same_csr_outstanding	18.250s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	4.849m	541.883us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	15.090s	13.494us	100	100	100.00
		xbar_smoke_large_delays	11.016m	2.987ms	100	100	100.00
		xbar_smoke_slow_rsp	10.518m	2.499ms	100	100	100.00
		xbar_random_zero_delays	2.312m	75.563us	100	100	100.00
		xbar_random_large_delays	36.955m	13.982ms	100	100	100.00
		xbar_random_slow_rsp	56.648m	14.877ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.606m	209.913us	100	100	100.00
		xbar_error_and_unmapped_addr	2.435m	220.905us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	4.051m	539.426us	100	100	100.00
		xbar_error_and_unmapped_addr	2.435m	220.905us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	7.902m	961.850us	100	100	100.00
		xbar_access_same_device_slow_rsp	58.701m	14.669ms	69	100	69.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	3.949m	428.828us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	32.765m	4.694ms	100	100	100.00
		xbar_stress_all_with_error	28.359m	4.016ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	52.524m	7.140ms	100	100	100.00
		xbar_stress_all_with_reset_error	55.205m	7.568ms	98	100	98.00
V2	rom_e2e_smoke	rom_e2e_smoke	16.747s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	15.104s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	17.480s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.280s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	14.582s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	15.199s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	15.742s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	14.004s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.894s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	15.877s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.412s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	15.169s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	14.846s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.653s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	18.227s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.768s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.648s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.203s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.566s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.904s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.210s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	19.127s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.262s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.683s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	14.660s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.932s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	15.612s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.329s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.691s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.154s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.773s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.826s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.033s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	15.433s		0	3	0.00
		rom_e2e_asm_init_dev	18.079s		0	3	0.00
		rom_e2e_asm_init_prod	16.541s		0	3	0.00
		rom_e2e_asm_init_prod_end	16.002s		0	3	0.00
		rom_e2e_asm_init_rma	16.972s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	15.980s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	17.015s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	16.191s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	17.333s		0	3	0.00
V2		TOTAL			1893	2429	77.93
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.272m	5.094ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.957m	4.597ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.338s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.793s		0	1	0.00
		rom_e2e_jtag_debug_rma	17.025s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	19.106s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	34.699m	17.034ms	92	100	92.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	19.348s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	22.617m	15.646ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	14.500s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	18.192s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.338s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.793s		0	1	0.00
		rom_e2e_jtag_debug_rma	17.025s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	14.607s		0	1	0.00
		rom_e2e_jtag_inject_dev	17.579s		0	1	0.00
		rom_e2e_jtag_inject_rma	17.586s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.926m		0	3	0.00
V3		TOTAL			1	20	5.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	27.071m	15.493ms	3	3	100.00
		chip_plic_all_irqs_0	13.316m	6.930ms	3	3	100.00
		chip_plic_all_irqs_10	14.367m	6.870ms	3	3	100.00
		chip_sw_dma_inline_hashing	7.708m	6.233ms	3	3	100.00
		chip_sw_dma_abort	5.997m	6.000ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	17.261s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	17.354s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	18.312s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	14.524s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	15.930s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	15.418s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	17.094s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	17.382s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	17.708s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	17.838s		0	3	0.00
		chip_sw_mbx_smoketest	7.010m	4.309ms	3	3	100.00
		TOTAL			2021	2659	76.01

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
75.55	74.55	78.12	66.02	--	80.90	66.93	86.79

Failure Buckets

Job returned non-zero exit code has 455 failures:

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.62362161966513306759780287469957654867100971095693840397423309737122987919421
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (ef7684)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 155.918s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_manufacturer.10929151403202931625372156754171491647987460372681566465336853509259098108054
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (04efb1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 25.254s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_data_integrity_escalation has 6 failures.

0.chip_sw_data_integrity_escalation.82965934520295908533594702577202558916550098742824107182375433320382011445005
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (1fac35)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 144.135s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_data_integrity_escalation.82823901988778194681123337074759403291633277103942777429188601771986013982826
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (718e6b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 9.764s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 4 more failures.

Test chip_sw_sleep_pin_wake has 3 failures.

0.chip_sw_sleep_pin_wake.105878090867275406858799570537822733420540568553169919891564574964649025124624
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b22a32)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 133.584s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_wake.1943669400532583614302119815351388826250887823595551447555519828032656198217
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (1a70f0)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 4.828s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_sleep_pin_retention has 3 failures.

0.chip_sw_sleep_pin_retention.38828388494107712226231405341310166132609559380091379156037885926837673290506
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (af258e)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 117.220s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_retention.14605941491642819758699727514265633913622015026110193477368717417256249089120
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (63a6c8)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 17.822s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_uart_tx_rx has 5 failures.

0.chip_sw_uart_tx_rx.33974275277738376962446160481249995788630349463830658855739963829849447031349
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (e39f92)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 112.094s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_uart_tx_rx.67746692453790899440717189248116508516592521640757608258475761216976639077706
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (8ab9bb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 5.149s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 3 more failures.

... and 131 more tests.

Job timed out after * minutes has 33 failures:
- Test xbar_access_same_device_slow_rsp has 31 failures.
  - 1.xbar_access_same_device_slow_rsp.826196495898174230693546812367511911721716512387023898924623085047919192214
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - 7.xbar_access_same_device_slow_rsp.69234788160892541912014426982617575688236405638746633570287976935628319356383
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/7.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 29 more failures.
- Test xbar_stress_all_with_reset_error has 2 failures.
  - 5.xbar_stress_all_with_reset_error.15021400925173379185756954417819263379983792120638589532409181440308743846847
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/5.xbar_stress_all_with_reset_error/latest/run.log
```
  Job timed out after 60 minutes
```
  - 83.xbar_stress_all_with_reset_error.78906850302817939657111558957893583480204351274455187697484300396484106809813
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/83.xbar_stress_all_with_reset_error/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 27 failures:
- Test chip_sw_aes_enc_jitter_en has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en.84815609009578788137911973866828105500276972721963943126165565995850368747848
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en.75876045311086397465698450082229604073598399284243079830213114523107657777272
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_hmac_enc_jitter_en has 3 failures.
  - 0.chip_sw_hmac_enc_jitter_en.239933253406860522804824123019174232922551627968268139039501451296031077286
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_enc_jitter_en.95725429963208532520861888035527745105402616831506424875126480732242538373153
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.73092622899737201863189014418216618322250838660374387010423183268159299363973
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.57413465926281875858086959672817831154375728934373631657505151685225101384718
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.106243754916685035595354754266170872244322382883738472460676628231847286417577
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_mode_kmac_jitter_en.13901249592677653599346123413125865463055719934042120711111344770569567666999
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.65159761908470909696774132401263842993623266861559354875060412652298185883521
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en_reduced_freq.33323401970318432967822720331778654991545158913568583446673173917014621386628
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 13 failures:

Test chip_sw_rstmgr_cpu_info has 3 failures.

0.chip_sw_rstmgr_cpu_info.78913022548607158073251847502357945567082915844490109854135101140497682826671
Line 500, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20023.792607 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20023.792607 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_cpu_info.69856376676633484905059500621645238510720062489155531161770973017274042639568
Line 481, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20017.157599 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20017.157599 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_irq has 3 failures.

0.chip_sw_aon_timer_irq.27460574116129187037031138218339266500375762785401007889052295525176067653904
Line 471, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.658499 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.658499 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_irq.63202844300652114935336544026801150679131504062295504525922170611768366131913
Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.185715 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.185715 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 5 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3991553489730548526450882906104605944338479051238830990495626784774365877567
Line 475, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18016.220353 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.220353 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_sleep_wdog_sleep_pause.40346595248174148265114043579032200002509777012247719053051532592230540454437
Line 465, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18014.442296 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18014.442296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

1.chip_sw_clkmgr_off_kmac_trans.113643892190807868735410510118941864320850292877001069646955112255950921245833
Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12025.069970 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12025.069970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

1.chip_sw_clkmgr_off_otbn_trans.80577897591833161388465644644023865998978676280452199696364885532392658937417
Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12014.868074 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.868074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 10 failures:

Test chip_sw_clkmgr_off_aes_trans has 3 failures.

0.chip_sw_clkmgr_off_aes_trans.19734836382862979414905247780139943171890353187177295915428558463866648068597
Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12015.121108 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.121108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_aes_trans.101767392952957253664806972673407335241308286161709965831679938214903603602211
Line 438, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12017.046853 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.046853 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_clkmgr_off_hmac_trans has 3 failures.

0.chip_sw_clkmgr_off_hmac_trans.9694718776759860846139709675370920156128000245925482892575287150315115041163
Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12015.227756 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.227756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_hmac_trans.61453163181745886021175636745614163819000957505774021519302078737234943000740
Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12022.625828 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12022.625828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_clkmgr_off_kmac_trans has 2 failures.

0.chip_sw_clkmgr_off_kmac_trans.71905210585589978710316373073574764962543499463152764758951053887897874440913
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12025.763495 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12025.763495 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_clkmgr_off_kmac_trans.31413869539327593594317857401527609115484641633296178016031712553618801245614
Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12014.546120 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.546120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 2 failures.

0.chip_sw_clkmgr_off_otbn_trans.48310409526132989336709036057839137167258633095355315853958837864068802149378
Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12016.291513 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.291513 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_clkmgr_off_otbn_trans.11664977570310693695105581131832036581207911755482687644785729702171359555950
Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12014.521090 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.521090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
- Test chip_padctrl_attributes has 10 failures.
  - 0.chip_padctrl_attributes.97444175653968962272965352399554275728847310225789472757509898326270710628733
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.chip_padctrl_attributes.33483921945373748896640011337403082687226376735150521831065926114014885773483
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.10882216807023906328185996240299969782554811660942034368230812683947842545480
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_bit_bash.1128495189578641067185554195498818194742350653355553320830451254261279974293
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.6894089760570282289850650950462593419646284623775760372758891541754524611685
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_aliasing.61415575035329130050787781752321094613641369180042227145637585980005492630275
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.27990538869522384482279327308351530984122850739950765513204642143021565017065
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_same_csr_outstanding.20017156879048511001169906241217092796877014498934439296571014093101886090209
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 8 failures:

Test chip_tl_errors has 8 failures.

6.chip_tl_errors.98763057713405768735619571658826093159592686815496123855470801738888477342435
Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_tl_errors/latest/run.log

      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4373.207168 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4373.207168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.chip_tl_errors.82717512226049758474796384844542830717403186808113338333997252323903305130940
Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_tl_errors/latest/run.log

      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3943.874636 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3943.874636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 6 failures:

Test chip_sw_keymgr_dpe_key_derivation has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation.60154025974218722383594727371820741090228290859076793874402073865777463309744
Line 482, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 5979.396280 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (99117496624601889378825340535506302110222481196846488340286230114647642768475 [0xdb2283d9350682309afdccedfde83f7120e6fe628628e00c21fa65d2cc94845b] vs 62781963450523899934554000800896745081051188322703334986771367167725516464487 [0x8acd5501d443eb0353e5be445bb2d2597c38191dc7d982f1f921303c18d1a167])
  UVM_INFO @ 5979.396280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation.104957281269419699869850076478140006408317067882056820621572286625145530317586
Line 473, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8308.911608 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (16422559876597459995519400798722191180964548081888589835858332202570226859281 [0x244ed6e90b0721f53b0bfc3a61f5874c4401008c5bb1956d2f9cfbc4d5dffd11] vs 60126462584916961671976274946032439104478909464710357248519570825835571369956 [0x84ee5f3063f888b089e4c9679b94e5e61f7032c378fecbefb5dfc43db194d7e4])
  UVM_INFO @ 8308.911608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.56415449347744152240747357856939028986202327407240266516873256221709687305001
Line 475, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7750.595628 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (3250938362679731122132603609774529785494401904176665136818023877386021833277 [0x72ff745b41d65344b4fde5cea85b7e067f00421b98ac62dac873fe903870a3d] vs 25399048196228256387827830921015794490383018761810501253488944036710283990568 [0x38275a11e91a874ce767ff67b992983631fffdd94369bfd2071b6b256327d628])
  UVM_INFO @ 7750.595628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation_prod.80397586532333750723473518440008620499711557284514877460844474948904367514203
Line 469, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 10004.395220 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (19654165646321071161242105849639818926471933196596244709774324178144582794765 [0x2b73dd110506d2a4e0fa55f7019ffe784d19d5928eaa8cf755c4a3004d457e0d] vs 47163115826677869830132967368483396612982203850505726406898638388142605118349 [0x684560a91955fb6b362bf9b60a494f1d14b02a384144216630cd44c52154ab8d])
  UVM_INFO @ 10004.395220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

Test chip_jtag_csr_rw has 3 failures.

0.chip_jtag_csr_rw.98404367021367771291876045342131292925603733622996104805440879861612335045155
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4551.828908 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hab802b3a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h1  a_user: 'h24890  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4551.828908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_csr_rw.90865424498709012002318310549076381997687123743881321232377980130669761129728
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3488.735266 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hdae7e305  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h0  a_user: 'h26970  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3488.735266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_jtag_mem_access has 3 failures.

0.chip_jtag_mem_access.45649209966678445205847540210194167753680125944725522897692280098505472577425
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3578.709035 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h282163d1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h0  a_user: 'h26932  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3578.709035 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_mem_access.30652664774869850296335884447493456069590217177886049176786490517185184943348
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3166.762058 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hb2a8f721  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h1  a_user: 'h248a5  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3166.762058 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_example_rom has 3 failures.
  - 0.chip_sw_example_rom.111243363738361351616614630628733291123100974015045411881933593310506359889357
    Line 626, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_example_rom.75513797222647011101023227469076739438496719049038306682447449315794476389795
    Line 394, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.97592182686046653469712098927670338587375039346889504597406339065542534698301
    Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3581.843200 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3581.843200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.64229761807726292276624654830637942687214392349463438790560247492013803783421
    Line 443, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3792.686800 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3792.686800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 3 failures:
- Test chip_sw_rstmgr_alert_info has 3 failures.
  - 0.chip_sw_rstmgr_alert_info.102745498685214288016944938812751620594771246323794795731271740755627875795656
    Line 684, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 9257.951750 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 9257.951750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rstmgr_alert_info.42741927495621540125953195771841657945085496345246598399973543416337588279196
    Line 692, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8069.254120 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8069.254120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 3 failures:

Test chip_sw_soc_proxy_external_alerts has 3 failures.

0.chip_sw_soc_proxy_external_alerts.2116196476712368936416979772940851822726123103000866586473603465116917364447
Line 481, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 4591.993874 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4591.993874 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_soc_proxy_external_alerts.2713598158349096926820086575494615822307721074938058397648407433890602607014
Line 448, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 3552.154534 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3552.154534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
- Test chip_sw_soc_proxy_external_wakeup has 3 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.76832057855780222379230188681923476194475968796179643310250635641374865270165
    Line 447, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4139.642568 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4139.642568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_soc_proxy_external_wakeup.95703655792084434040692636105794087901105352188686026589383123837122735914226
    Line 457, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5100.670650 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5100.670650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 3 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.55487041367913545274449471839283302005736417909479369618840142168268116885071
    Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4050.125066 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4050.125066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aon_timer_wdog_bite_reset.74858713447939007748555516133359198641945602392503887221038529599028218739580
    Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 6032.624496 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 6032.624496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.38930109156157657561714940532752544089078254671982310980807600589440357487182
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5508.844432 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5508.844432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rv_core_ibex_nmi_irq.6887177344056625940848500051257119407092005907852067854464469415172948210006
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6605.419872 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6605.419872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_kmac_app_rom has 3 failures.
  - 0.chip_sw_kmac_app_rom.1023226184049691693422443980134810470997475593945988975576146976502247961545
    Line 447, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_app_rom.55882171862109453004499711492463153658745826270849302162245495947640061328881
    Line 443, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 3 failures:
- Test chip_rv_dm_ndm_reset_req has 3 failures.
  - 0.chip_rv_dm_ndm_reset_req.807939846918967323596749670415189255468025511172079768796957491525355182181
    Line 411, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13939.817860 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13939.817860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_rv_dm_ndm_reset_req.44339839592384666462747437379167659786982990036003132739128603430248258347278
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14121.875590 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14121.875590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 3 failures:

Test chip_sw_dma_abort has 3 failures.

0.chip_sw_dma_abort.44551369060036355749421653781754469695563683290276791267152356932595218511065
Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4467.851802 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4467.851802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_dma_abort.5302491608674933099352761745483938338495251600201239773795596399642686099243
Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4831.770592 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4831.770592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (sec_cm_pkg.sv:53) [sec_cm_pkg] find_sec_cm_if_proxy: no proxy with path *otp_ctrl.u_otp.*u_state_regs has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 1.chip_sw_all_escalation_resets.12579201159891916271632658787948344652969046527313440664485355648827594260498
    Line 461, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.320001 us: (sec_cm_pkg.sv:53) [sec_cm_pkg] find_sec_cm_if_proxy: no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 78.chip_sw_all_escalation_resets.98955195203968515516564115365815691309006314857360246736606221172993522109908
    Line 408, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/78.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.320001 us: (sec_cm_pkg.sv:53) [sec_cm_pkg] find_sec_cm_if_proxy: no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 17.chip_sw_all_escalation_resets.15276025541490151905953837324766001952264698271418832593294586483540510105004
    Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 4155.327852 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 4155.327852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 25.chip_sw_all_escalation_resets.67571010956942102947822974368694081910611368498180508571060159621100427778467
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 4552.857376 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 4552.857376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:

Test chip_sw_all_escalation_resets has 2 failures.

45.chip_sw_all_escalation_resets.45706602725740131554029628382217806127656009646172886778284036896768313761782
Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest/run.log

  UVM_ERROR @ 12010.100001 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

90.chip_sw_all_escalation_resets.28996865830868875188276501517832998840048908796797709373937939299230230667533
Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest/run.log

  UVM_ERROR @ 12010.360001 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35870) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures: