AES/MASKED Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: `22488a4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	153.397us	1	1	100.00
V1	smoke	aes_smoke	7.000s	171.826us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	101.281us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	67.139us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.985ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	86.328us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	118.849us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	67.139us	20	20	100.00
		aes_csr_aliasing	7.000s	86.328us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	171.826us	50	50	100.00
		aes_config_error	18.000s	1.962ms	50	50	100.00
		aes_stress	44.000s	3.274ms	50	50	100.00
V2	key_length	aes_smoke	7.000s	171.826us	50	50	100.00
		aes_config_error	18.000s	1.962ms	50	50	100.00
		aes_stress	44.000s	3.274ms	50	50	100.00
V2	back2back	aes_stress	44.000s	3.274ms	50	50	100.00
		aes_b2b	22.000s	672.220us	50	50	100.00
V2	backpressure	aes_stress	44.000s	3.274ms	50	50	100.00
V2	multi_message	aes_smoke	7.000s	171.826us	50	50	100.00
		aes_config_error	18.000s	1.962ms	50	50	100.00
		aes_stress	44.000s	3.274ms	50	50	100.00
		aes_alert_reset	15.000s	867.282us	50	50	100.00
V2	failure_test	aes_man_cfg_err	7.000s	189.396us	50	50	100.00
		aes_config_error	18.000s	1.962ms	50	50	100.00
		aes_alert_reset	15.000s	867.282us	50	50	100.00
V2	trigger_clear_test	aes_clear	36.000s	1.639ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	1.411ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	15.000s	867.282us	50	50	100.00
V2	stress	aes_stress	44.000s	3.274ms	50	50	100.00
V2	sideload	aes_stress	44.000s	3.274ms	50	50	100.00
		aes_sideload	17.000s	767.044us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	658.006us	50	50	100.00
V2	stress_all	aes_stress_all	50.000s	5.274ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	67.368us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	239.012us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	239.012us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	101.281us	5	5	100.00
		aes_csr_rw	5.000s	67.139us	20	20	100.00
		aes_csr_aliasing	7.000s	86.328us	5	5	100.00
		aes_same_csr_outstanding	6.000s	114.147us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	101.281us	5	5	100.00
		aes_csr_rw	5.000s	67.139us	20	20	100.00
		aes_csr_aliasing	7.000s	86.328us	5	5	100.00
		aes_same_csr_outstanding	6.000s	114.147us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.750m	6.483ms	50	50	100.00
V2S	fault_inject	aes_fi	22.000s	1.707ms	50	50	100.00
		aes_control_fi	43.000s	10.003ms	285	300	95.00
		aes_cipher_fi	46.000s	10.004ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	137.327us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	137.327us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	137.327us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	137.327us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	108.815us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.398ms	5	5	100.00
		aes_tl_intg_err	7.000s	1.695ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	1.695ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	15.000s	867.282us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	137.327us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	171.826us	50	50	100.00
		aes_stress	44.000s	3.274ms	50	50	100.00
		aes_alert_reset	15.000s	867.282us	50	50	100.00
		aes_core_fi	45.000s	10.004ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	137.327us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	105.252us	50	50	100.00
		aes_stress	44.000s	3.274ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	44.000s	3.274ms	50	50	100.00
		aes_sideload	17.000s	767.044us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	105.252us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	105.252us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	105.252us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	105.252us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	105.252us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	44.000s	3.274ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	44.000s	3.274ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	22.000s	1.707ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	22.000s	1.707ms	50	50	100.00
		aes_control_fi	43.000s	10.003ms	285	300	95.00
		aes_cipher_fi	46.000s	10.004ms	336	350	96.00
		aes_ctr_fi	6.000s	60.497us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	22.000s	1.707ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	22.000s	1.707ms	50	50	100.00
		aes_control_fi	43.000s	10.003ms	285	300	95.00
		aes_cipher_fi	46.000s	10.004ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.004ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	22.000s	1.707ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	22.000s	1.707ms	50	50	100.00
		aes_control_fi	43.000s	10.003ms	285	300	95.00
		aes_ctr_fi	6.000s	60.497us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	22.000s	1.707ms	50	50	100.00
		aes_control_fi	43.000s	10.003ms	285	300	95.00
		aes_cipher_fi	46.000s	10.004ms	336	350	96.00
		aes_ctr_fi	6.000s	60.497us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	15.000s	867.282us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	22.000s	1.707ms	50	50	100.00
		aes_control_fi	43.000s	10.003ms	285	300	95.00
		aes_cipher_fi	46.000s	10.004ms	336	350	96.00
		aes_ctr_fi	6.000s	60.497us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	22.000s	1.707ms	50	50	100.00
		aes_control_fi	43.000s	10.003ms	285	300	95.00
		aes_cipher_fi	46.000s	10.004ms	336	350	96.00
		aes_ctr_fi	6.000s	60.497us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	22.000s	1.707ms	50	50	100.00
		aes_control_fi	43.000s	10.003ms	285	300	95.00
		aes_ctr_fi	6.000s	60.497us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	22.000s	1.707ms	50	50	100.00
		aes_control_fi	43.000s	10.003ms	285	300	95.00
		aes_cipher_fi	46.000s	10.004ms	336	350	96.00
V2S		TOTAL			952	985	96.65
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	35.000s	2.576ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1559	1602	97.32

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.59	96.43	99.40	95.68	98.07	97.78	99.11	98.39

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 11.aes_cipher_fi.68066872188307860228130140916036017175924603580476743435397745007016069591243
    Line 137, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003930981 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003930981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 16.aes_cipher_fi.70408131285277519022384979594697528461281852135533139962009278298996328913524
    Line 144, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007022135 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007022135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 40.aes_control_fi.82729770595490357754050839944401676657246452926273922605716956748892101200369
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10040413081 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10040413081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 61.aes_control_fi.5150900943182450229494313965889983760178923346357106402759220268993321209366
    Line 143, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/61.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002767330 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002767330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
Job timed out after * minutes has 8 failures:
- Test aes_cipher_fi has 1 failures.
  - 52.aes_cipher_fi.15553815553670850837698131333532675730419093178436908371092118176594923298597
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_control_fi has 7 failures.
  - 58.aes_control_fi.82672839899041333751899716943464402435147044051178454718974332106211046237441
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 65.aes_control_fi.17054332809686248891380413190609934692292251606108027637811807239451436485831
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/65.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

3.aes_stress_all_with_rand_reset.81829319936052072400906900460396530799330577142887119243188990687646214738141
Line 192, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  71523843 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  71523843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.107994975285402000611806695959852510913574116456033048167724279845967257727743
Line 213, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  65425701 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  65425701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 11.aes_core_fi.79369183576930253549630854689373919623358960170874202650549355880378263140151
    Line 146, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003630054 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003630054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.aes_core_fi.41231846027964839364351428809529067991165490415310188616869688173169229401206
    Line 131, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009324638 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009324638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.86948795554563759687822498613348012453188496812149000291391033307937487145787
    Line 825, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4961029919 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 4961029919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.aes_stress_all_with_rand_reset.34615303803053982741739298097688909548049281810329371526120854297367407159291
    Line 620, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2615624455 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2615624455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.88050299911051512367019129366790723153371381132086157170749662719655860107146
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  24612138 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  24612138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```